Display driver integrated circuit and driving method

    公开(公告)号:US11295677B2

    公开(公告)日:2022-04-05

    申请号:US17208206

    申请日:2021-03-22

    Abstract: A display driver integrated circuit includes a first memory, a compensator, an accumulator and a second memory. The first memory stores a plurality of compensation data that are used to compensate for deterioration of a plurality of pixels. The compensator generates a plurality of output image data for image display by compensating a plurality of input image data based on the plurality of compensation data. The accumulator groups the plurality of pixels into a plurality of blocks, generates a plurality of block image data by sampling the plurality of output image data in block units, generates a plurality of block accumulation data in block units based on the plurality of block image data, and generates a plurality of pixel accumulation data in pixel units by synthesizing portions of the plurality of output image data and portions of the plurality of block accumulation data. The second memory stores the plurality of block accumulation data in a first period. The plurality of pixel accumulation data may be stored in a third memory in a second period longer than the first period.

    Receiver circuit performing adaptive equalization and system including the same

    公开(公告)号:US11223468B1

    公开(公告)日:2022-01-11

    申请号:US17194831

    申请日:2021-03-08

    Abstract: A receiver circuit includes an equalizer configured to generate an equalization signal by equalizing an input data signal transferred through a communication channel based on an equalization coefficient; a clock data recovery circuit configured to generate a data clock signal and an edge clock signal based on the equalization signal, generate a data sample signal including a plurality of data bits by sampling the equalization signal in synchronization with the data clock signal, and generate an edge sample signal including a plurality of edge bits by sampling the equalization signal in synchronization with the edge clock signal; and an equalization control circuit configured to control the equalization coefficient by comparing the plurality of data bits and the plurality of edge bits.

    CLOCK AND DATA RECOVERY CIRCUIT AND A DISPLAY APPARATUS HAVING THE SAME

    公开(公告)号:US20210067310A1

    公开(公告)日:2021-03-04

    申请号:US16878728

    申请日:2020-05-20

    Abstract: A display device including: a timing controller outputting a reference clock signal and a data packet, wherein the data, packet includes a clock signal embedded in a data signal; a clock and data recovery (CDR) circuit receiving the reference clock signal and the data packet; and a display panel displaying an image based on the data packet, wherein, when the CDR circuit receives the reference clock signal, a frequency band of the reference clock signal is detected using a first internal clock signal, a parameter associated with jitter characteristics of the clock and data recovery circuit is adjusted according to the detected frequency band, and a second internal clock signal is output by adjusting a frequency of the first internal clock signal and when the CDR circuit receives the data packet, the data signal and a clock signal synchronized with the data signal are recovered from the data packet.

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