公开(公告)号：US11437105B2

公开(公告)日：2022-09-06

申请号：US17234955

申请日：2021-04-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yohan Lee ,  Sangwan Nam ,  Sangwon Park

IPC: G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/04 ,  G11C16/32 ,  G11C16/08 ,  G11C16/30

Abstract: A memory device includes memory blocks, each including memory cells, and peripheral circuits that control the memory blocks and execute an erase operation for each of the memory blocks. Each memory block includes word lines stacked on a substrate, channel structures extending perpendicular to an upper surface of the substrate and penetrating through the word lines, and a source region disposed on the substrate and connected to the channel structures. During an erase operation in which an erase voltage is input to the source region of a target memory block, the peripheral circuits reduce a voltage of a first word line from a first bias voltage to a second bias voltage at a first time and reduce a voltage of a second word line, different from the first word line, from a third bias voltage to a fourth bias voltage at a second time different from the first in time.

公开(公告)号：US11355205B2

公开(公告)日：2022-06-07

申请号：US17172288

申请日：2021-02-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangwon Shim ,  Sangwon Park ,  Bongsoon Lim ,  Yoonhee Choi

IPC: G11C16/30 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  G11C5/14

Abstract: A memory device includes a first memory area including a first memory cell array having a plurality of first memory cells and a first peripheral circuit disposed below the first memory cell array; a second memory area including a second memory cell array having a plurality of second memory cells and a second peripheral circuit disposed below the second memory cell array; and a pad area including a power wiring. The first and second memory areas respectively include first and second local lockout circuits separately determining whether to lock out of each of the memory areas. The first and second memory areas are included in a single semiconductor chip to share the pad area, and the first and second memory areas operate individually. Accordingly, in the memory device, unnecessary data loss may be reduced by selectively stopping an operation of only a memory area requiring recovery.

公开(公告)号：US11056200B2

公开(公告)日：2021-07-06

申请号：US17012135

申请日：2020-09-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiyeon Shin ,  Sangwan Nam ,  Sangwon Park

IPC: G11C7/00 ,  G11C16/34 ,  H01L27/11526 ,  H01L27/11573 ,  H01L27/1157 ,  G11C16/26 ,  H01L27/11524 ,  H01L27/11556 ,  G11C16/10 ,  H01L27/11582

Abstract: Method of controlling initialization of nonvolatile memory device, where nonvolatile memory device includes memory cell region including first metal pad and peripheral circuit region including second metal pad and vertically connected to memory cell region by first and second metal pads, includes performing first sensing operation to sense write setting data stored in first memory cells in memory cell region of first memory plane and store first read setting data in first page buffer circuit in peripheral circuit region of first memory plane, performing second sensing operation to sense write setting data stored in second memory cells in memory cell region of second memory plane and store second read setting data in second page buffer circuit in peripheral circuit region of second memory plane and performing dump-down operation to store restored setting data in buffer based on first read setting data and second read setting data.

公开(公告)号：US20140254702A1

公开(公告)日：2014-09-11

申请号：US14201600

申请日：2014-03-07

Applicant: INDUSTRY-ACADEMIC COOPERATION FOUNDATION,YONSEI UNIVERSITY ,  Samsung Electronics Co., Ltd.

Inventor： Hyojin Lee ,  Chungyong Lee ,  Hoondong Nho ,  Younsun Kim ,  Juho Lee ,  Hyoungju Ji ,  Sangwon Park ,  Ilgyu Choi

IPC: H04B7/04 ,  H04L5/00

CPC classification number: H04B7/0456 ,  H04B7/0617 ,  H04B7/0619 ,  H04B7/0639 ,  H04B7/0658 ,  H04L25/0204 ,  H04L25/0228

Abstract: The present disclosure relates to a method and an apparatus for transmitting and receiving channel related information. A method of transmitting channel related information of a UE according to an embodiment of the present disclosure includes configuring a sub-channel corresponding to a part of a plurality of antennas of an eNB; acquiring a Channel Estimation Error (CEE) and a Precoding Matrix Indicator (PMI) corresponding to the sub-channel; and transmitting a Sub-channel Indicator (SI) indicating the sub-channel, according to the CEE and the PMI. In accordance with an embodiment of the present disclosure, the channel related information is efficiently transmitted and received in a system in which a plurality of antennas is used.

Abstract translation: 本公开涉及一种用于发送和接收信道相关信息的方法和装置。 根据本公开的实施例的发送UE的信道相关信息的方法包括配置与eNB的多个天线的一部分相对应的子信道; 获取对应于子信道的信道估计误差（CEE）和预编码矩阵指示符（PMI）; 以及根据CEE和PMI发送指示子信道的子信道指示符（SI）。 根据本公开的实施例，信道相关信息在其中使用多个天线的系统中被有效地发送和接收。