公开(公告)号：US09761320B1

公开(公告)日：2017-09-12

申请号：US15383852

申请日：2016-12-19

Applicant: SanDisk Technologies LLC

Inventor： Hong-Yan Chen ,  Ching-Huang Lu ,  Wei Zhao

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/28 ,  G11C16/16 ,  G11C16/10

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3427 ,  G11C16/3459

Abstract: A memory device and associated techniques for reducing read disturb of memory cells during the last phase of a sensing operation when all voltage signals are ramped down to a steady state voltage. In one aspect, the voltages of the source side word line, WL0, and an adjacent dummy word line, WLDS1, are ramped down after the voltages of remaining word lines are ramped down. This can occur regardless of whether WL0 is the selected word line which is programmed or read. The technique can be applied after the sensing which occurs in a read or program-verify operation. Another option involves elevating the voltage of the selected word line so that all word lines are ramped down from the same level, such as a read pass level. The techniques are particularly useful when the memory device includes an interface in the channel between epitaxial silicon and polysilicon.