公开(公告)号：US20220406383A1

公开(公告)日：2022-12-22

申请号：US17352095

申请日：2021-06-18

Applicant: SanDisk Technologies LLC

Inventor： Henry Chin ,  Hua-Ling Cynthia Hsu ,  Wei Zhao ,  Fanglin Zhang

IPC: G11C16/14 ,  G11C16/26 ,  G11C16/34 ,  G06F1/20

Abstract: Techniques disclosed herein cope with temperature effects in non-volatile memory systems. A control circuit is configured to sense a current temperature of the memory system and read, verify, program, and erase data in non-volatile memory cells by modifying one or more read/verify/program/erase parameters based on a temperature compensation value. The control circuit is further configured to read, verify, program, and erase data by accessing a historical temperature value stored in the memory system, the historical temperature value comprising a temperature at which a previous read, verify, program or erase occurred and measuring a current temperature value. The control circuit determines the temperature compensation value by applying a smoothing function. The smoothing function determines the temperature compensation value by selecting either the historical temperature value or the current temperature value as the temperature compensation value based on a difference between the historical temperature value and the current temperature relative to a threshold, or calculating the temperature compensation value, different from the current temperature value or the historical temperature value, based a smoothing function which utilizes the current temperature value and the historical temperature value.

公开(公告)号：US11063063B2

公开(公告)日：2021-07-13

申请号：US16710481

申请日：2019-12-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yanli Zhang ,  Dong-il Moon ,  Raghuveer S. Makala ,  Peng Zhang ,  Wei Zhao ,  Ashish Baraskar

IPC: H01L29/76 ,  H01L27/11582 ,  H01L27/11556 ,  H01L23/532 ,  H01L21/311 ,  H01L27/11526 ,  H01L27/11565 ,  H01L27/11573 ,  H01L21/28 ,  H01L23/528 ,  H01L27/11519

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, and memory stack structures extending through the alternating stack. Each of the memory stack structures contains a memory film and a vertical semiconductor channel. At least one of the electrically conductive layers contains a first conductive material portion having a respective inner sidewall that contacts a respective one of the memory films at a vertical interface, and a second conductive material portion that has a different composition from the first conductive material portion, and contacting the first electrically conductive material portion. The first conductive material portion has a lower work function than the second conductive material portion.

公开(公告)号：US10559370B2

公开(公告)日：2020-02-11

申请号：US15928976

申请日：2018-03-22

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Piyush Dak ,  Wei Zhao ,  Huai-Yuan Tseng ,  Deepanshu Dutta ,  Mohan Dunga

IPC: G11C16/06 ,  G11C16/34 ,  G11C16/32 ,  G11C16/26 ,  G11C16/10 ,  G11C16/24 ,  G11C11/56 ,  G11C16/04

Abstract: A circuit includes a detection circuit configured to determine a capacitance delay (RC-delay) in an initial stage of a read or program operation and to adjust timing for detecting data in a subsequent stage, or portion of a stage, of the same read or programming operation. In particular, during a program operation a detection circuit may be configured to detect a pre-charge time for a bit line and adjust a timing of subsequent verify stages of the bit line during the same program operation based on the detected pre-charge time. Additionally, a word line circuit may be configured to detect a pre-charge time for a word line during an initial stage of a read operation and adjust read timing for a subsequent portion of the same read stage, or subsequent read stage of the read operation based on the detected word line pre-charge time.

公开(公告)号：US20190295669A1

公开(公告)日：2019-09-26

申请号：US15928976

申请日：2018-03-22

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Piyush Dak ,  Wei Zhao ,  Huai-Yuan Tseng ,  Deepanshu Dutta ,  Mohan Dunga

IPC: G11C16/34 ,  G11C16/32 ,  G11C16/26 ,  G11C16/10

Abstract: A circuit includes a detection circuit configured to determine a capacitance delay (RC-delay) in an initial stage of a read or program operation and to adjust timing for detecting data in a subsequent stage, or portion of a stage, of the same read or programing operation. In particular, during a program operation a detection circuit may be configured to detect a pre-charge time for a bit line and adjust a timing of subsequent verify stages of the bit line during the same program operation based on the detected pre-charge time. Additionally, a word line circuit may be configured to detect a pre-charge time for a word line during an initial stage of a read operation and adjust read timing for a subsequent portion of the same read stage, or subsequent read stage of the read operation based on the detected word line pre-charge time.

公开(公告)号：US20190074062A1

公开(公告)日：2019-03-07

申请号：US15694008

申请日：2017-09-01

Applicant: SanDisk Technologies LLC

Inventor： Hong-Yan Chen ,  Wei Zhao ,  Ching-Huang Lu ,  Yingda Dong

IPC: G11C16/08 ,  G11C16/04

Abstract: A memory device and associated techniques for reducing read disturb of memory cells during a sensing process. Select gate transistors are transitioned to a conductive state one or more time during a sensing process, at the drain and/or source ends of the memory strings in an unselected sub-block. The transitioning can occur periodically, multiple times during the sensing process. When the select gate transistors are in a conductive state, accumulated holes in the channel can be removed. This help provide a faster decrease of the channel potential when the unselected word line voltages are ramped down at the end of the sensing process. The duration of a disturb-inducing channel gradient which is created next to the edge data memory cell is reduced so that read disturb of this cell is also reduced.

公开(公告)号：US12057161B2

公开(公告)日：2024-08-06

申请号：US17847698

申请日：2022-06-23

Applicant: SanDisk Technologies LLC

Inventor： Wei Zhao ,  Dong-II Moon ,  Erika Penzo ,  Henry Chin

IPC: G11C16/04 ,  G11C11/56 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C11/5642 ,  G11C11/5628 ,  G11C11/5671 ,  G11C16/10 ,  G11C16/26

Abstract: The memory device includes a plurality of memory blocks that can individually operate in either a multi-bit per memory cell mode or a single-bit per memory cell mode. Certain voltage parameters during programming and reading are shared between these two operating modes, and certain voltage parameters are unique to each operating mode. One unique voltage parameter is a pass voltage VREADK that is applied to word lines adjacent a selected word line being read. Another unique voltage parameter is a VSGD voltage that is applied to a select gate drain transistor during programming. Yet another unique voltage parameter is an inhibit voltage that is applied to a bit line coupled with a memory cell being inhibited from programming while other memory cells are programmed.

公开(公告)号：US11972810B2

公开(公告)日：2024-04-30

申请号：US17845430

申请日：2022-06-21

Applicant: SanDisk Technologies LLC

Inventor： Han-Ping Chen ,  Wei Zhao ,  Henry Chin

IPC: G11C11/34 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34

CPC classification number: G11C16/3436 ,  G11C16/08 ,  G11C16/102 ,  G11C16/26

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected word lines. The memory cells are disposed in strings and configured to retain a threshold voltage. A control means is configured to apply a program voltage to selected ones of the word lines while applying pass voltages to unselected ones of the word lines and ramp down both the selected ones of the plurality of word lines and the unselected ones of the word lines to a recovery voltage at a start of a verify phase of each of a plurality of program loops and apply a targeted word line bias to each of the word lines during the verify phase. The control means is also configured to adjust the recovery voltage based on the targeted word line bias applied to each of the plurality of word lines during the verify phase.

公开(公告)号：US20230420053A1

公开(公告)日：2023-12-28

申请号：US17846452

申请日：2022-06-22

Applicant: SanDisk Technologies LLC

Inventor： Xuan Tian ,  Henry Chin ,  Liang Li ,  Vincent Yin ,  Wei Zhao ,  Tony Zou

IPC: G11C16/14 ,  G11C16/04 ,  G11C16/24 ,  G11C16/08 ,  G11C16/26 ,  G11C16/34 ,  G11C29/50

CPC classification number: G11C16/14 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/08 ,  G11C16/26 ,  G11C16/349 ,  G11C29/50004 ,  H01L27/11556

Abstract: The memory device includes a memory block with an array of memory cells. The memory device also includes control circuitry that is in communication with the memory cells. The control circuitry is configured to program a group of the memory cells in a programming operation that does not include verify to obtain a natural threshold voltage (nVt) distribution, calculate an nVt width of the nVt distribution, compare the nVt width to a threshold, and identify the memory block as being vulnerable to cross-temperature read errors in response to the nVt width exceeding the threshold.

公开(公告)号：US20230420042A1

公开(公告)日：2023-12-28

申请号：US17847698

申请日：2022-06-23

Applicant: SanDisk Technologies LLC

Inventor： Wei Zhao ,  Dong-II Moon ,  Erika Penzo ,  Henry Chin

IPC: G11C11/56 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C11/5642 ,  G11C11/5628 ,  G11C11/5671 ,  G11C16/10 ,  G11C16/26

Abstract: The memory device includes a plurality of memory blocks that can individually operate in either a multi-bit per memory cell mode or a single-bit per memory cell mode. Certain voltage parameters during programming and reading are shared between these two operating modes, and certain voltage parameters are unique to each operating mode. One unique voltage parameter is a pass voltage VREADK that is applied to word lines adjacent a selected word line being read. Another unique voltage parameter is a VSGD voltage that is applied to a select gate drain transistor during programming. Yet another unique voltage parameter is an inhibit voltage that is applied to a bit line coupled with a memory cell being inhibited from programming while other memory cells are programmed.

公开(公告)号：US20230410923A1

公开(公告)日：2023-12-21

申请号：US17845318

申请日：2022-06-21

Applicant: SanDisk Technologies LLC

Inventor： Wei Zhao ,  Henry Chin

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/24

CPC classification number: G11C16/3459 ,  G11C16/102 ,  G11C16/14 ,  G11C16/26 ,  G11C16/24

Abstract: A storage device comprises: a non-volatile memory including control circuitry and an array of memory cells formed using a set of word lines and a set of bit lines. A controller, coupled to the non-volatile memory, configured to: during a program loop for programming a set of states, select a first bitline biasing mode that dictates a scheme for biasing a first set of bitlines and apply the first bitline biasing mode before verifying the set of states. The controller further configured to during another program loop for programming another set of states, select a second bitline biasing mode that dictates a scheme for biasing a second set of bitlines and apply the second bitline biasing mode before verifying the other set of states.