Abstract:
A processor executes a predetermined operation process by switching a connection structure between a plurality of arithmetic and logic unit modules. Each of the arithmetic and logic unit modules includes a plurality of arithmetic and logic units. The arithmetic and logic unit modules include a first arithmetic and logic unit module that includes a plurality of arithmetic and logic units that executes various operation processes, and a second arithmetic and logic unit module that includes a plurality of arithmetic and logic units of which executable operation processes are limited compared with the first arithmetic and logic unit module.
Abstract:
A service identification adding portion adds service identification information to a cell corresponding to each connection that uses a predetermined communication service (ABR service) and that is input to a switch system. A connection number counting portion counts the number of connections that use the communication service on each output line at predetermined intervals. A band control information generating portion generates band control information corresponding to each output line at predetermined intervals based on the number of connections counted at predetermined intervals. A band control information indicating portion sends band control information at predetermined intervals corresponding to each output line to a transmission side terminal corresponding to a connection that uses the communication service on each output line.
Abstract:
A switching system in an ATM switching system accommodating an ABR is constructed of an individual units connected to a transmitting terminal or a receiving terminal to implement an efficient bandwidth authorization, and a plurality of intra-system relay devices having transmission allowed rate calculating units. In this switching system, there are separated a transfer of a management cell between the transmitting terminal or the receiving terminal and the individual unit and a transfer of the management cell between the plurality of intra-system relay devices.
Abstract:
An operation apparatus includes a sequencer controlling states of a plurality of operation devices and a configuration memory storing therein configuration information as setting information for each state in the operation device. In the operation apparatus, a path which requires a data buffer and another path which requires no such a data buffer are provided for inputting data to the operation device, a data buffer control part is provided for controlling selection from these two paths and operation of the data buffer, and contents of path selection and operation control of the data buffer carried out by the data buffer control part are set according to the configuration information.
Abstract:
An operation apparatus includes a sequencer controlling states of a plurality of operation devices and a configuration memory storing therein configuration information as setting information for each state in the operation device. In the operation apparatus, a path which requires a data buffer and another path which requires no such a data buffer are provided for inputting data to the operation device, a data buffer control part is provided for controlling selection from these two paths and operation of the data buffer, and contents of path selection and operation control of the data buffer carried out by the data buffer control part are set according to the configuration information.
Abstract:
A peripheral device cable, connected to a peripheral device, integrally incorporates a subscriber link that is a physical line for transmitting subscriber information in synchronization with a highway clock and a control link that is a physical line for transmitting control data in synchronization with the highway clock. A control data converter controls interfacing between the control data transferred over the control link synchronously with the highway clock and control data that a control unit transmits/receives asynchronously with the highway clock. The subscriber link is connected to a switch.
Abstract:
A cell count identifier inserting portion for inserting a cell count identifier into the header portion of a cell is provided at a predetermined position within an exchange and a plurality of cell counting portions for counting a cell into which a cell count identifier is inserted are provided on the downstream side of the cell count identifier inserting portion. A cell loss detecting portion compares the number of cells into which the cell count identifier is inserted with the number of cells counted by each of the cell counting portions, detects cell loss on the basis of the result of the comparisons and specifies the section in which cell loss is caused, if the cell loss is detected.