Suppression of noise between phase lock loops in a selective call
receiver and method therefor
    31.
    发明授权
    Suppression of noise between phase lock loops in a selective call receiver and method therefor 失效
    选择呼叫接收机中锁相环之间的噪声抑制及其方法

    公开(公告)号:US6064869A

    公开(公告)日:2000-05-16

    申请号:US33011

    申请日:1998-03-02

    摘要: A synthesizer (100) is used for generating a plurality of synthesized clock signals (128, 156). The synthesizer includes a clock source (102) for generating a common frequency reference signal (103), and a clock generator (104) coupled to the common frequency reference signal for generating a plurality of generated clock signals (106, 108), wherein each of the plurality of generated clock signals is offset from each other by a predetermined phase offset (189, 192). In addition, the synthesizer includes a plurality of PLLs (Phase Locked Loops) (166-168) for generating a selected one of the plurality of synthesized clock signals, wherein each of the plurality of PLLs is coupled to, and operates from, a corresponding one of the plurality of generated clock signals, and wherein the predetermined phase offset between each of the plurality of generated clock signals is known to suppress noise between the plurality of PLLs operating therefrom.

    摘要翻译: 合成器(100)用于产生多个合成时钟信号(128,156)。 合成器包括用于产生公共频率参考信号(103)的时钟源(102)和耦合到公共频率参考信号的时钟发生器(104),用于产生多个产生的时钟信号(106,108),其中每个 多个生成的时钟信号彼此偏移了预定的相位偏移(189,192)。 另外,合成器包括多个PLL(锁相环)(166-168),用于产生多个合成时钟信号中选择的一个,其中多个PLL中的每一个耦合到相应的 多个生成的时钟信号中的一个,并且其中已知多个所生成的时钟信号中的每一个之间的预定相位偏移,以抑制从其操作的多个PLL之间的噪声。

    Linear low noise phase-frequency detector
    32.
    发明授权
    Linear low noise phase-frequency detector 有权
    线性低噪声相位检波器

    公开(公告)号:US6002273A

    公开(公告)日:1999-12-14

    申请号:US166756

    申请日:1998-10-05

    IPC分类号: H03L7/089 H03L7/197 H03D13/00

    CPC分类号: H03L7/1976 H03L7/0891

    摘要: A phase-frequency detector (110) includes an output stage (300) and a control stage (200). The output stage includes a pump up switched current source (350), a pump down switched current sink (360), and a constant current source (325) that are coupled to a charge pump output node (111). The control stage generates, in response to a divided variable frequency signal (FV) (136) and a reference frequency signal (FR) (106), a pump up control signal (246) and a pump down control signal (216).

    摘要翻译: 相位频率检测器(110)包括输出级(300)和控制级(200)。 输出级包括耦合到电荷泵输出节点(111)的泵浦开关电流源(350),抽运开关电流吸收器(360)和恒定电流源(325)。 控制级响应于分压的可变频率信号(FV)(136)和参考频率信号(FR)(106),产生泵浦控制信号(246)和抽空控制信号(216)。