-
公开(公告)号：US6100730A
公开(公告)日：2000-08-08
申请号：US201015
申请日：1998-11-30
CPC分类号： H03K3/356121
摘要： A prescaler system (100) has a prescaler circuit (102) coupled to a divider (104), wherein the divider includes an improved dynamic flip flop divider (118). The divider (118) includes a TSPC nine-transistor D-flip-flop (10). The divider further includes a tenth transistor such as N channel device (41) having a source coupled to ground (43), a drain coupled to a junction between a drain of a P channel device (34) and a drain of another N channel device (37). The divider also includes an eleventh transistor such as N channel device (42) having a source coupled to ground and a drain coupled to a junction between the drain of a P channel device (35) and the drain of a N channel device (39), the junction providing a feedback signal to a N channel device (36), wherein the eleventh transistor further has a gate coupled to the output signal (/Q.sub.A).
摘要翻译： 预分频器系统（100）具有耦合到分频器（104）的预分频器电路（102），其中分频器包括改进的动态触发器分频器（118）。 分压器（118）包括TSPC九晶体管D触发器（10）。 分压器还包括第十晶体管，例如具有耦合到地（43）的源极的N沟道器件（41），耦合到P沟道器件（34）的漏极与另一N沟道器件的漏极之间的结的漏极 （37）。 分压器还包括第十一晶体管，例如具有耦合到地的源极的N沟道器件（42）和耦合到P沟道器件（35）的漏极与N沟道器件（39）的漏极之间的结的漏极， ，所述接点向N沟道器件（36）提供反馈信号，其中所述第十一晶体管还具有耦合到所述输出信号（/ QA）的栅极。
-
2.发明授权Frequency prescaler method and apparatus responsive to low input drive levels 失效响应于低输入驱动电平的频率预分频器方法和装置
公开(公告)号：US5939911A
公开(公告)日：1999-08-17
申请号：US033619
申请日：1998-03-05
摘要： A low input prescaler (800) that is responsive to input signals having low amplitude alternating current (AC) components includes a switched tunable prescaler (280) that generates a prescaler output signal (221) having a prescaler output frequency during an operational state of the prescaler and having a free-running frequency that is responsive to a tuning control signal (216) during a tuning state of the prescaler. A frequency comparator (235) generates a comparator output in response to a difference between a reference frequency and the prescaler output frequency. A prescaler tuner (290, 390) adjusts the tuning control signal in response to the comparator output during the tuning state to minimize the difference between the reference frequency and the prescaler output frequency, and holds the tuning control signal during the operational state. The prescaler is used in phase lock loops (200, 400, 600) and other circuits.
摘要翻译： 响应于具有低振幅交流（AC）分量的输入信号的低输入预分频器（800）包括一个开关可调预分频器（280），其产生一个预分频器输出信号（221），该预分频器预分频器在操作状态期间具有预分频器输出频率 预分频器，并且在预分频器的调谐状态期间具有响应于调谐控制信号（216）的自由运行频率。 频率比较器（235）响应于参考频率和预分频器输出频率之间的差产生比较器输出。 在调谐状态期间，预分频调谐器（290,390）响应于比较器输出来调整调谐控制信号，以最小化参考频率和预分频器输出频率之间的差异，并且在操作状态期间保持调谐控制信号。 预分频器用于锁相环（200,400,600）和其他电路。
-
3.发明授权Suppression of noise between phase lock loops in a selective call receiver and method therefor 失效选择呼叫接收机中锁相环之间的噪声抑制及其方法
公开(公告)号：US6064869A
公开(公告)日：2000-05-16
申请号：US33011
申请日：1998-03-02
CPC分类号： H03L7/07 , H03L7/23 , H04B15/04 , H04B2215/064
摘要： A synthesizer (100) is used for generating a plurality of synthesized clock signals (128, 156). The synthesizer includes a clock source (102) for generating a common frequency reference signal (103), and a clock generator (104) coupled to the common frequency reference signal for generating a plurality of generated clock signals (106, 108), wherein each of the plurality of generated clock signals is offset from each other by a predetermined phase offset (189, 192). In addition, the synthesizer includes a plurality of PLLs (Phase Locked Loops) (166-168) for generating a selected one of the plurality of synthesized clock signals, wherein each of the plurality of PLLs is coupled to, and operates from, a corresponding one of the plurality of generated clock signals, and wherein the predetermined phase offset between each of the plurality of generated clock signals is known to suppress noise between the plurality of PLLs operating therefrom.
摘要翻译： 合成器（100）用于产生多个合成时钟信号（128,156）。 合成器包括用于产生公共频率参考信号（103）的时钟源（102）和耦合到公共频率参考信号的时钟发生器（104），用于产生多个产生的时钟信号（106,108），其中每个 多个生成的时钟信号彼此偏移了预定的相位偏移（189,192）。 另外，合成器包括多个PLL（锁相环）（166-168），用于产生多个合成时钟信号中选择的一个，其中多个PLL中的每一个耦合到相应的 多个生成的时钟信号中的一个，并且其中已知多个所生成的时钟信号中的每一个之间的预定相位偏移，以抑制从其操作的多个PLL之间的噪声。
-
公开(公告)号：US08857983B2
公开(公告)日：2014-10-14
申请号：US13358579
申请日：2012-01-26
申请人： Randall Braxton Pugh , Daniel B. Otts , Frederick A. Flitsch , Adam Toner , Scott Robert Humphreys
发明人： Randall Braxton Pugh , Daniel B. Otts , Frederick A. Flitsch , Adam Toner , Scott Robert Humphreys
CPC分类号： G02C7/049 , A61F2/1624 , A61F2250/0001 , A61F2250/0002 , B29D11/00038 , B29D11/00817 , G02C7/04 , G02C7/083 , H01Q1/22 , H01Q1/2225 , H01Q7/00
摘要： Antennas and antenna systems may be designed and configured for incorporation into mechanical devices, including medical devices, such as ophthalmic devices, including contact lenses. These antennas and antenna systems may be utilized to transmit data from the mechanical device to a receiver, to receive data from a transmitter, and/or to inductively charge an electromechanical cell or the like incorporated into the mechanical device.
摘要翻译： 天线和天线系统可以被设计和配置成并入到机械装置中，包括医疗装置，诸如眼科装置，包括隐形眼镜。 这些天线和天线系统可用于将数据从机械设备传送到接收机，从发射机接收数据，和/或感应地对组装在机械设备中的机电电池等进行充电。
-
公开(公告)号：US20130343248A1
公开(公告)日：2013-12-26
申请号：US13531874
申请日：2012-06-25
申请人： Adam Toner , Scott Robert Humphreys , Randall Braxton Pugh , Daniel B. Otts , William Chester Neeley
发明人： Adam Toner , Scott Robert Humphreys , Randall Braxton Pugh , Daniel B. Otts , William Chester Neeley
IPC分类号： H04W52/02
CPC分类号： H04W56/0085 , Y02D70/00 , Y02D70/26
摘要： A wireless protocol for a communication system is set forth herein which may be utilized for communication between a transmitter and a receiver over any type of communication channel. The wireless communication protocol provides for the reduction of receiver active or on time which in turn lowers power consumption. The wireless communication protocol enables the complexity and receiver size to be reduced. The methodology employed in the protocol utilizes a unique message frame in conjunction with repeated transmission and periodic receiver searching.
摘要翻译： 本文阐述了用于通信系统的无线协议，其可以用于任何类型的通信信道上的发射机和接收机之间的通信。 无线通信协议提供减少接收器的有效或准时，从而降低功耗。 无线通信协议使复杂度和接收机尺寸得以减小。 在协议中使用的方法利用独特的消息帧结合重复的传输和周期性的接收机搜索。
-
公开(公告)号：US20110038488A1
公开(公告)日：2011-02-17
申请号：US12851200
申请日：2010-08-05
IPC分类号： H04B3/00
CPC分类号： G10H1/0083
摘要： A wireless musical instrument network (400, 500) may comprise one or more wireless link modules (100, 200, 300). In some embodiments a first wireless link module may be adapted to receive a first input audio signal and transmit a first wireless signal having a modulation component based on the first input audio signal. A second wireless link module may be adapted to receive the first wireless signal and a second input audio signal. The second wireless link module may be further adapted to demodulate the first wireless signal to provide a first received audio signal, and combine the first received audio signal and the second input audio signal to provide a combined audio signal. The second wireless link module may provide a second wireless signal having a modulation component based on the combined audio signal, whereby the combined audio signal and the second wireless signal contain information based on both the first input audio signal and the second input audio signal
摘要翻译： 无线乐器网络（400,500）可以包括一个或多个无线链路模块（100,200,300）。 在一些实施例中，第一无线链路模块可以适于接收第一输入音频信号，并且基于第一输入音频信号发送具有调制分量的第一无线信号。 第二无线链路模块可以适于接收第一无线信号和第二输入音频信号。 第二无线链路模块还可以适于解调第一无线信号以提供第一接收音频信号，并且组合第一接收音频信号和第二输入音频信号以提供组合音频信号。 第二无线链路模块可以提供具有基于组合音频信号的调制分量的第二无线信号，由此组合音频信号和第二无线信号基于第一输入音频信号和第二输入音频信号两者包含信息
-
7.发明授权公开(公告)号：US06724265B2
公开(公告)日：2004-04-20
申请号：US10172627
申请日：2002-06-14
IPC分类号： H03L700
CPC分类号： H03L7/1974 , H03L7/0898
摘要： A system is provided for compensating for tuning gain variations in a phase lock loop. Compensation is performed by a calibration system that estimates the tuning gain of the oscillator and then adjusts the charge pump current value by a ratio of the nominal tuning gain to the measured tun gain. The tuning gain measurement is performed by measuring the change in the voltage controlled oscillator's tuning control voltage when the phase lock loop is locked to two different frequencies, which are separated by a fixed, predetermined amount. The two frequencies may be above or below the final output frequency of the VCO, or the second frequency may be the final frequency in order to reduce calibration time and settling time.
摘要翻译： 提供了一种用于补偿锁相环中的调谐增益变化的系统。 通过校准系统进行补偿，该校准系统估计振荡器的调谐增益，然后通过额定调谐增益与测量的脉冲增益的比值来调整电荷泵电流值。 调谐增益测量是通过测量当锁相环锁定到两个不同频率的压控振荡器的调谐控制电压的变化来进行的，这两个频率被固定的预定量分开。 两个频率可以高于或低于VCO的最终输出频率，或者第二频率可以是最终频率，以便减少校准时间和稳定时间。
-
公开(公告)号：US08068573B1
公开(公告)日：2011-11-29
申请号：US11740967
申请日：2007-04-27
摘要： The present invention is a phase dithered digital communications system that includes a digital receiver, and uses phase dithering to spread the energy of one or more system clocks to minimize receiver de-sensitization. Phase dithering uses a single frequency for each system clock; however, the energy of each system clock is spread over a range of frequencies by changing the duty-cycle of each clock half-cycle. A non-phase dithered clock drives the sampling clock of a receiver analog-to-digital converter to provide accurate correlation with received information, which may allow use of a higher frequency sampling clock than in frequency dithered designs. Phase dithered clocks and non-phase dithered clocks may have constant frequencies that are related to each other by a ratio of two integers; therefore, the time base used for extracting received data is always correlated and accurate.
摘要翻译： 本发明是一种相位抖动数字通信系统，其包括数字接收机，并且使用相位抖动来扩展一个或多个系统时钟的能量以最小化接收机去敏感。 相位抖动对每个系统时钟使用单个频率; 然而，每个系统时钟的能量通过改变每个时钟半周期的占空比在一个频率范围内扩展。 非相抖动时钟驱动接收器模拟 - 数字转换器的采样时钟，以提供与接收信息的精确相关性，这可能允许使用比在频率抖动设计中更高频率的采样时钟。 相位抖动时钟和非相位抖动时钟可以具有通过两个整数的比率彼此相关的恒定频率; 因此，用于提取接收到的数据的时基总是相关和准确的。
-
9.发明授权System and method for transitioning from one PLL feedback source to another 有权从一个PLL反馈源转换到另一个PLL反馈源的系统和方法公开(公告)号：US07412215B1
公开(公告)日：2008-08-12
申请号：US11144119
申请日：2005-06-03
IPC分类号： H04B1/04
CPC分类号： H04B1/0475 , H03L7/081 , H03L7/087 , H03L7/16 , H03L2207/12
摘要： A system and method are provided for switching from one phase-locked loop feedback source to another in a radio frequency (RF) transmitter. The RF transmitter includes a phase-locked loop (PLL) that provides a phase-modulated RF input signal and power amplifier circuitry that amplifies the RF input signal to provide an RF output signal. The PLL includes switching circuitry that couples a feedback path of the PLL to an output of the PLL for open loop operation and couples the feedback path of the PLL to an output of the power amplifier circuitry for closed loop operation. Prior to switching the feedback path from the output of the PLL to the output of the power amplifier circuitry, time alignment circuitry operates to time-align feedback signals from the outputs of the PLL and the power amplifier circuitry such that switching from open loop operation to closed loop operation causes minimal phase disturbance.
摘要翻译： 提供了一种用于在射频（RF）发射机中从一个锁相环反馈源切换到另一个的系统和方法。 RF发射器包括提供相位调制RF输入信号的锁相环（PLL）和放大RF输入信号以提供RF输出信号的功率放大器电路。 PLL包括将PLL的反馈路径耦合到PLL的输出以用于开环操作的开关电路，并将PLL的反馈路径耦合到用于闭环操作的功率放大器电路的输出。 在将反馈路径从PLL的输出切换到功率放大器电路的输出之前，时间对准电路用于对来自PLL和功率放大器电路的输出的反馈信号进行时间对准，使得从开环操作切换到 闭环运行导致最小的相位扰动。
-
10.发明授权Pre-distortion system for a synthesizer having modulation applied in the reference path 有权具有在参考路径中应用的调制的合成器的预失真系统公开(公告)号：US07288999B1
公开(公告)日：2007-10-30
申请号：US11347956
申请日：2006-02-06
CPC分类号： H03L7/1976 , H03C3/0966 , H03L7/23 , H03L2207/12
摘要： A system providing a phase or frequency modulated signal is provided. In general, the system includes a phase locked loop (PLL) having a fractional-N divider in a reference path of the PLL operating to divide a reference frequency based on a pre-distorted modulation signal. Pre-distortion circuitry operates to provide the pre-distorted modulation signal by pre-distorting a modulation signal such that a convolution, or cascade, of the pre-distortion and a transfer function of the PLL results in a substantially flat frequency response for a range of modulation rates greater than a bandwidth of the PLL.
摘要翻译： 提供了提供相位或频率调制信号的系统。 通常，该系统包括在PLL的参考路径中具有分数N分频器的锁相环（PLL），其操作以基于预失真调制信号来划分参考频率。 预失真电路通过对调制信号进行预失真来提供预失真调制信号，使得预失真和PLL的传递函数的卷积或级联导致范围内的基本平坦的频率响应 的调制率大于PLL的带宽。
-
-
-
-
-
-
-
-
-
搜索结果
32 条记录 (耗时 0.022 秒)
