公开(公告)号：US20050146657A1

公开(公告)日：2005-07-07

申请号：US10907053

申请日：2005-03-18

Applicant: Chi-Jain Wen ,  Dai-Liang Ting ,  Hsiao-Yi Lin ,  Gwo-Long Lin ,  I-Wei Wu

Inventor： Chi-Jain Wen ,  Dai-Liang Ting ,  Hsiao-Yi Lin ,  Gwo-Long Lin ,  I-Wei Wu

IPC: G02F1/1335 ,  G02F1/1362

CPC classification number: G02F1/133555 ,  G02F1/13624

Abstract: A transflective liquid crystal display (LCD) includes at least a transmission pixel region and at least a reflection pixel region positioned in a pixel region. The transmission region includes at least a transmissive electrode connected to a first switching element. The reflection pixel region includes at least a reflective electrode connected to a second switching element. The transmissive and the reflective electrodes are controlled respectively by independent switching elements.

Abstract translation: 半透射型液晶显示器（LCD）至少包括透射像素区域和至少位于像素区域中的反射像素区域。 透射区域至少包括连接到第一开关元件的透射电极。 反射像素区域至少包括连接到第二开关元件的反射电极。 透射和反射电极分别由独立的开关元件控制。

公开(公告)号：US20050067626A1

公开(公告)日：2005-03-31

申请号：US10945673

申请日：2004-09-20

Applicant: Hsiao-Yi Lin

Inventor： Hsiao-Yi Lin

IPC: G02F1/136 ,  G02F1/1368 ,  H01L21/00 ,  H01L21/77 ,  H01L27/12 ,  H01L27/15 ,  H01L31/12 ,  H01L31/153 ,  H01L33/00

CPC classification number: G02F1/1368 ,  G02F2202/104 ,  H01L27/12 ,  H01L27/1248

Abstract: An LCD having semiconductor components. In one embodiment of the invention, the structure with multiple silicon layers comprises a substrate, a first silicon layer on the substrate, a gate dielectric layer on the first silicon layer, a gate on the gate dielectric layer, an interlayer dielectric layer on the gate, and a second silicon layer on the interlayer dielectric layer.

Abstract translation: 具有半导体元件的LCD。 在本发明的一个实施例中，具有多个硅层的结构包括衬底，衬底上的第一硅层，第一硅层上的栅极电介质层，栅极电介质层上的栅极，栅极上的层间介质层 ，以及层间电介质层上的第二硅层。

公开(公告)号：US20050036581A1

公开(公告)日：2005-02-17

申请号：US10917695

申请日：2004-08-12

Applicant: Hsiao-Yi Lin

Inventor： Hsiao-Yi Lin

IPC: G11C8/04 ,  G11C19/00 ,  G11C19/28

CPC classification number: G11C19/00 ,  G11C8/04 ,  G11C19/28

Abstract: A shift register unit. The shift register unit outputs a shift register signal according to a clock signal, an inverse clock signal and a start signal. The shift register has first and second clock inversion circuits, and an inverter. In the first clock inversion circuit, a third PMOS transistor has a third source coupled to the first voltage, a third gate and a third drain. A fourth PMOS transistor has a fourth source coupled to the third drain, a fourth gate and a fourth drain coupled to the second voltage. A fifth PMOS transistor has a fifth source coupled to the third drain, a fifth drain coupled to the first gate, and a fifth gate. A sixth PMOS transistor having a sixth source coupled to the third gate, a sixth drain coupled to the second gate, and a sixth gate coupled to the fifth gate.

Abstract translation: 移位寄存器单元。 移位寄存器单元根据时钟信号，反时钟信号和起始信号输出移位寄存器信号。 移位寄存器具有第一和第二时钟反相电路以及反相器。 在第一时钟反相电路中，第三PMOS晶体管具有耦合到第一电压的第三源极，第三栅极和第三漏极。 第四PMOS晶体管具有耦合到第三漏极的第四源极，耦合到第二电压的第四栅极和第四漏极。 第五PMOS晶体管具有耦合到第三漏极的第五源极，耦合到第一栅极的第五漏极和第五栅极。 第六PMOS晶体管，具有耦合到第三栅极的第六源极，耦合到第二栅极的第六漏极和耦合到第五栅极的第六栅极。

公开(公告)号：US06803263B1

公开(公告)日：2004-10-12

申请号：US10420453

申请日：2003-04-22

Applicant: Hsiao-Yi Lin ,  Wei Chih Chang

Inventor： Hsiao-Yi Lin ,  Wei Chih Chang

IPC: H01L2100

CPC classification number: H01L29/66757 ,  H01L29/78621

Abstract: A method of fabricating a thin film transistor (TFT) with self-aligned structure. A substrate is provided, with a semiconductor layer and gate insulation layer formed in sequence thereon, followed by formation of a conductive layer on the gate insulation layer, and definition of the conductive layer to form a gate conductive layer and a dummy conductive layer. The dummy conductive layer is on both sides of the gate conductive layer and provided with a gap therebetween. A first ion implantation is performed via the gap to form a lightly doped region on the semiconductor layer thereunder, and a sacrificial layer is formed to fill the gap. The dummy conductive layer is removed. The gate conductive layer and the remaining sacrificial layer are used as a mask. Finally, a second ion implantation is performed to form a heavily doped source/drain region on the semiconductor layer.

Abstract translation: 一种制造具有自对准结构的薄膜晶体管（TFT）的方法。 提供了一种衬底，其上依次形成半导体层和栅极绝缘层，随后在栅极绝缘层上形成导电层，并且定义导电层以形成栅极导电层和虚拟导电层。 虚设导电层位于栅极导电层的两侧，并在它们之间具有间隙。 通过间隙进行第一离子注入，以在其之后的半导体层上形成轻掺杂区域，形成牺牲层以填充间隙。 去除虚拟导电层。 栅极导电层和剩余的牺牲层用作掩模。 最后，进行第二离子注入以在半导体层上形成重掺杂的源/漏区。