公开(公告)号：US06344395B1

公开(公告)日：2002-02-05

申请号：US09624324

申请日：2000-07-24

申请人： Chih-Jen Huang ,  Chia-Te Wu

发明人： Chih-Jen Huang ,  Chia-Te Wu

IPC分类号： H01L21336

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11546

摘要： A method for fabricating a non-volatile memory on the semiconductor substrate is disclosed. First of all, a plurality of trench isolation regions are formed. Then, firstly implanting ions of a first conductivity type and second conductivity type are carried out. Secondly implanting ions of the first conductivity type and second conductivity type are carried out. Then, a first oxide layer is deposited and the first oxide layer is removed. A second oxide layer is deposited. A portion of second oxide is removed, thus, a portion of second oxide layer is remained. A third oxide layer is formed. A first polysilicon layer is formed. The first polysilicon layer is etched. A oxide-nitride-oxide layer is formed. Consequentially, the oxide-nitride-oxide layer are all etched. The second polysilicon on is formed. A portion of the second polysilicon layer, a portion of the first polysilicon layer, a portion of the third oxide layer and a portion of the second oxide layer are all etched. Thus, capacitor columns are formed.

摘要翻译： 公开了一种用于在半导体衬底上制造非易失性存储器的方法。 首先，形成多个沟槽隔离区域。 然后，首先进行第一导电型和第二导电型的离子注入。 其次，进行第一导电型和第二导电型的离子注入。 然后，沉积第一氧化物层并除去第一氧化物层。 沉积第二氧化物层。 第二氧化物的一部分被去除，因此残留了第二氧化物层的一部分。 形成第三氧化物层。 形成第一多晶硅层。 蚀刻第一多晶硅层。 形成氧化物 - 氮化物 - 氧化物层。 因此，氧化物 - 氮化物 - 氧化物层全部被蚀刻。 形成第二个多晶硅。 第二多晶硅层的一部分，第一多晶硅层的一部分，第三氧化物层的一部分和第二氧化物层的一部分全部被蚀刻。 因此，形成电容器列。

公开(公告)号：US06258667B1

公开(公告)日：2001-07-10

申请号：US09386672

申请日：1999-08-31

申请人： Chih-Jen Huang

发明人： Chih-Jen Huang

IPC分类号： H01L218247

CPC分类号： H01L27/11526 ,  H01L27/11546 ,  Y10S438/952

摘要： A method for implementing embedded flash is disclosed. The embedded flash, which comprises memory cells and logic peripherals, is formed on a substrate where a gate oxide layer, a tunneling oxide layer and a floating gate are performed. The spirit of the invention is that transistors of the cell region and transistors of the peripheral region are implemented separated. In the proposed method, after transistors of the peripheral region are totally formed, then formation of transistors of the cell region begins to perform. Therefore, not only material of spacers of transistors of peripheral region, but also silicides can only be formed on the peripheral region and on the gate transistors of the cell region. Beside, ARC layer are fabricated on the embedded flash before spacers of transistors of cell region are fabricated. Thus, for memory cells, issues of both junction breakdown voltage and junction leakage also is not degraded by silicides. In comparison, for logic peripherals, performances are enhanced by spacers of transistors are formed by nitride and proper silicides.

摘要翻译： 公开了一种实现嵌入式闪存的方法。 包括存储器单元和逻辑外围设备的嵌入式闪存形成在执行栅极氧化物层，隧道氧化物层和浮动栅极的衬底上。 本发明的精神在于，单元区域的晶体管和外围区域的晶体管分开实现。 在所提出的方法中，在外围区域的晶体管完全形成之后，开始形成单元区域的晶体管。 因此，不仅可以在周边区域和单元区域的栅极晶体管上形成外围区域的晶体管的间隔物的材料，而且还可以形成硅化物。 除此之外，在制造在单元区域的晶体管的间隔物之前，在嵌入式闪存上制造ARC层。 因此，对于存储器单元，两个结击穿电压和结漏电的问题也不会被硅化物降解。 相比之下，对于逻辑外围设备，通过氮化物和合适的硅化物形成晶体管的间隔物来增强性能。

公开(公告)号：US06228718B1

公开(公告)日：2001-05-08

申请号：US09468558

申请日：1999-12-21

申请人： Chih-Jen Huang ,  Shih-Fang Hong

发明人： Chih-Jen Huang ,  Shih-Fang Hong

IPC分类号： H01L218247

CPC分类号： H01L27/11521

摘要： The present invention is a method of fabricating a self-aligned split gate of flash memory. Aligned layers are formed on predetermined source regions and predetermined drain regions in advance. Spacers are formed on the sidewalls of the aligned layers. An etching rate of the spacers is different from an etching rate of the aligned layers. Therefore, if misalignment occurs during the patterning process to form a split control gate layer, the spacers also can be left after the aligned layer is removed. The remaining spacers serves as a implant mask during the implantion for the sources and the drains formation, so that the sources and the drains are formed in the respective positions of the aligned layers by self-alignment.

摘要翻译： 本发明是制造闪存的自对准分裂门的方法。 对准层预先在预定的源极区域和预定的漏极区域上形成。 间隔物形成在对准层的侧壁上。 间隔物的蚀刻速率与对准层的蚀刻速率不同。 因此，如果在形成分割控制栅极层的图案化工艺期间发生不对准，则在去除对准层之后也可以留下间隔物。 剩余的间隔物在用于源和漏极形成的植入期间用作植入物掩模，使得源和漏极通过自对准形成在对准层的相应位置。

公开(公告)号：US08552490B2

公开(公告)日：2013-10-08

申请号：US12818176

申请日：2010-06-18

申请人： Chih-Jen Huang ,  Chien-Hung Chen

发明人： Chih-Jen Huang ,  Chien-Hung Chen

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545

摘要： A nonvolatile memory device and a manufacturing method thereof are provided. The manufacturing method includes the following steps. First, a substrate is provided. Then, a tunneling dielectric layer is formed on the substrate, and a dummy gate is form on the tunneling dielectric layer. Subsequently, an interlayer dielectric layer is formed around the dummy gate, and the dummy gate is removed to form an opening. Following that, a charge storage layer is formed on the inner side wall of the opening, and the charge storage layer covers the tunneling dielectric layer. Moreover, an inter-gate dielectric layer is formed on the charge storage layer, and a metal gate is formed on the inter-gate dielectric layer. Accordingly, a stacked gate structure of the nonvolatile memory device includes the tunneling dielectric layer, the charge storage layer, the inter-gate dielectric layer, and the metal gate.

摘要翻译： 提供了一种非易失性存储器件及其制造方法。 该制造方法包括以下步骤。 首先，提供基板。 然后，在衬底上形成隧道电介质层，并在隧道电介质层上形成虚拟栅极。 随后，在虚拟栅极周围形成层间电介质层，并且去除虚拟栅极以形成开口。 之后，在开口的内侧壁上形成电荷存储层，电荷存储层覆盖隧道电介质层。 此外，在电荷存储层上形成栅极间电介质层，在栅极间电介质层上形成金属栅极。 因此，非易失性存储器件的堆叠栅极结构包括隧道电介质层，电荷存储层，栅极间电介质层和金属栅极。

公开(公告)号：US08204827B1

公开(公告)日：2012-06-19

申请号：US12056608

申请日：2008-03-27

申请人： Diwakar Gupta ,  Chih-Jen Huang ,  Philip Yuen ,  Gerald Yuen

发明人： Diwakar Gupta ,  Chih-Jen Huang ,  Philip Yuen ,  Gerald Yuen

IPC分类号： G06Q40/00

CPC分类号： G06Q20/10 ,  G06F9/451 ,  G06Q40/12

摘要： Various embodiments of a system and method for personalized commands are described. The system and method for personalized commands may include a payment service including a command management component. Such payment service may be responsive to one or more base commands. The command management component may be configured to generate a user interface for specifying personalized commands that correspond to the base commands. The command management component may be configured to generate mapping information from the information received via the user interface. The command management component may be configured to receive one or more messages that may include commands for the payment service, including personalized commands. From the personalized commands, the command management component may be configured to determine a corresponding base commands (e.g., based on the mapping information). Once the base command is determined, the payment service may perform the base command.

摘要翻译： 描述用于个性化命令的系统和方法的各种实施例。 用于个性化命令的系统和方法可以包括包括命令管理组件的支付服务。 这种支付服务可以响应于一个或多个基本命令。 命令管理组件可以被配置为生成用于指定与基本命令相对应的个性化命令的用户界面。 命令管理组件可以被配置为从经由用户界面接收的信息生成映射信息。 命令管理组件可以被配置为接收可包括用于支付服务的命令的一个或多个消息，包括个性化命令。 根据个性化命令，命令管理组件可以被配置为确定相应的基本命令（例如，基于映射信息）。 一旦确定了基本命令，支付服务就可以执行基本命令。

公开(公告)号：US20090159966A1

公开(公告)日：2009-06-25

申请号：US11960723

申请日：2007-12-20

申请人： Chih-Jen Huang

发明人： Chih-Jen Huang

IPC分类号： H01L27/088 ,  H01L21/8234

CPC分类号： H01L21/76229 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/82385 ,  H01L21/823857 ,  H01L21/823878 ,  H01L29/1037 ,  H01L29/42372 ,  H01L29/6659 ,  H01L29/66621

摘要： A high voltage semiconductor device comprises a substrate, a well, a gate structure, and a source/drain structure in a grade region in a well in the substrate. The gate structure is disposed on the substrate with a portion vertically down into a trench in the well in the substrate and has a relatively small size. The method of fabricating the high voltage semiconductor device comprises forming a first trench for an STI structure and a second trench for a gate structure, depositing an oxide layer on the substrate to fill the first and the second trenches, wherein a void is formed in the second trench, performing a photolithography and etching process to remove a portion of the oxide layer in the second trench, and forming a gate on the gate dielectric layer in the second trench.

摘要翻译： 高压半导体器件包括衬底，阱，栅极结构以及衬底中的阱中的等级区域中的源极/漏极结构。 栅极结构设置在衬底上，其一部分垂直向下放置在衬底中的阱中的沟槽中并且具有相对较小的尺寸。 制造高电压半导体器件的方法包括形成用于STI结构的第一沟槽和用于栅极结构的第二沟槽，在衬底上沉积氧化物层以填充第一和第二沟槽，其中在 第二沟槽，执行光刻和蚀刻工艺以去除第二沟槽中的氧化物层的一部分，以及在第二沟槽中的栅极电介质层上形成栅极。

公开(公告)号：US20090096039A1

公开(公告)日：2009-04-16

申请号：US11870243

申请日：2007-10-10

申请人： Chih-Jen Huang ,  Shih-Ming Hsu

发明人： Chih-Jen Huang ,  Shih-Ming Hsu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7835 ,  H01L29/0634 ,  H01L29/66659

摘要： A high-voltage device including a first conductive type substrate, a gate, a second conductive type well, a second conductive type source region, a second conductive type drain region, conductive layers, and a first conductive type top layer. The gate is disposed on the substrate, and the well is disposed in the substrate at one side of the gate. The source region is disposed in the substrate at the other side of the gate. The drain region is disposed in the well of the substrate. The conductive layers are disposed on the substrate between the gate and the drain region. The top layer is disposed in the well of the substrate, and the well is below the conductive layers. One portion of the top layer near the gate has a thickness greater than that of the other portion of the top layer away from the gate.

摘要翻译： 一种包括第一导电型基板，栅极，第二导电型阱，第二导电型源极区域，第二导电型漏极区域，导电层和第一导电型顶层的高压器件。 栅极设置在衬底上，并且阱在栅极的一侧设置在衬底中。 源极区域设置在栅极的另一侧的衬底中。 漏极区域设置在衬底的阱中。 导电层设置在栅极和漏极区域之间的衬底上。 顶层设置在衬底的阱中，并且阱在导电层之下。 栅极附近的顶层的一部分的厚度大于离开栅极的顶层的另一部分的厚度。

公开(公告)号：US07251653B2

公开(公告)日：2007-07-31

申请号：US10880888

申请日：2004-06-30

申请人： Chih-Jen Huang ,  Steven Sheldon ,  Robert Turner ,  Patrick Conlan

发明人： Chih-Jen Huang ,  Steven Sheldon ,  Robert Turner ,  Patrick Conlan

IPC分类号： G06F17/30 ,  G06F7/00

CPC分类号： G06F17/30619 ,  G06F17/30943 ,  Y10S707/99936 ,  Y10S707/99953

摘要： The mapping system maps a physical table of a database to a logical table representing a logical view of the database that integrates standard columns and custom columns. The physical table includes a standard table with standard columns and a custom table with custom columns. The custom table may be implemented as a pivot table. The mapping system provides a map between standard and custom columns and logical columns. The physical table may include multiple standard tables. The mapping system allows for individual standard tables to be updated, rather than updating all the columns across all the standard tables for a row.

摘要翻译： 映射系统将数据库的物理表映射到表示集成标准列和自定义列的数据库的逻辑视图的逻辑表。 物理表包括带有标准列的标准表和具有自定义列的自定义表。 自定义表可以实现为枢轴表。 映射系统提供了标准列和自定义列与逻辑列之间的映射。 物理表可以包括多个标准表。 映射系统允许更新单个标准表，而不是更新一行的所有标准表中的所有列。

公开(公告)号：US20070094150A1

公开(公告)日：2007-04-26

申请号：US11546534

申请日：2006-10-10

申请人： Philip Yuen ,  Chih-Jen Huang ,  Gerald Yuen

发明人： Philip Yuen ,  Chih-Jen Huang ,  Gerald Yuen

IPC分类号： G06Q99/00 ,  H04L9/00 ,  H04K1/00

CPC分类号： G06Q20/04 ,  G06Q20/02 ,  G06Q20/0855 ,  G06Q20/3674 ,  G06Q20/382 ,  G06Q20/401 ,  G06Q20/4012

摘要： System and method for authorizing transactions, such as payments or money transfers. A source entity may initiate a transaction with a target entity via a first communications channel. In initiating the transaction, the source entity may indicate that the transaction is to be performed through a transaction authorization service. The target entity may send a transaction initiation message to the transaction authorization service. In response to receiving the transaction initiation message, the service may authorize the transaction with the source entity via a second communications channel. To authorize the transaction, the source entity may provide a PIN number or other identifier via the second communications channel. After receiving and validating the response from the source entity, the transaction authorization service may inform the target entity that the transaction is authorized. The target entity may then complete the transaction with the transaction authorization service and the source entity.

摘要翻译： 授权交易的系统和方法，如付款或汇款。 源实体可以经由第一通信信道发起与目标实体的交易。 在发起交易时，源实体可以指示将通过交易授权服务来执行交易。 目标实体可以向事务授权服务发送事务发起消息。 响应于接收到交易发起消息，服务可以经由第二通信信道授权与源实体的交易。 为了授权交易，源实体可以经由第二通信信道提供PIN号码或其他标识符。 交易授权服务器在接收到来自源实体的响应和验证后，可以向目标实体通知交易被授权。 然后，目标实体可以与事务授权服务和源实体完成事务。

公开(公告)号：US20060146848A1

公开(公告)日：2006-07-06

申请号：US11026501

申请日：2004-12-30

申请人： Jack Kirstein ,  Chih-Jen Huang ,  Pradeep Ganapathyraj ,  Sharry Claypool

发明人： Jack Kirstein ,  Chih-Jen Huang ,  Pradeep Ganapathyraj ,  Sharry Claypool

IPC分类号： H04L12/56

CPC分类号： H04L69/40 ,  H04L47/50 ,  Y10S707/99938 ,  Y10S707/99943 ,  Y10S707/99945

摘要： A queuing server is used for reliable message transport, where one subsystem desires to execute one or more ordered operations asynchronously. Messages are sent to the queue in groups, which may have one or more messages. Messages within a particular group are processed in a predetermined order. Optionally, groups of messages can marked as correlated such that all groups within a particular correlation can be processed in a predetermined order. A message can be stored in a SQL database table until processing of that message is complete. The receiving side of the message system can be scaled across multiple machines and/or across available resources of any given machine. The system can handle “disaster” scenarios on both the sending side (i.e. the sending machine crashes in the middle of sending a group), and the receiving side (i.e., a power failure causes a reboot in at least one of the receiving machines).