CAPACITIVE PRESSURE SENSOR IN AN OVERMOLDED PACKAGE
    31.
    发明申请
    CAPACITIVE PRESSURE SENSOR IN AN OVERMOLDED PACKAGE 有权
    过压封装中的电容式压力传感器

    公开(公告)号:US20140033814A1

    公开(公告)日:2014-02-06

    申请号:US13562853

    申请日:2012-07-31

    IPC分类号: H01L29/84 B60C23/04 H01L21/50

    摘要: An overmolded pressure sensor package is provided. The pressure sensor die (Pcell) is capped so that the Pcell has enhanced rigidity to withstand stress effects produced by the molding encapsulant. The Pcell cap includes a hole located away from the Pcell diaphragm, so that external gas pressure can be experienced by the Pcell, while at the same time directing moisture away from the diaphragm. Gel does not need to be used, and instead a soft film can be deposited on the Pcell to protect the Pcell diaphragm from excess moisture, if needed. The Pcell cap can take the form of, for example, a dummy silicon wafer or a functional ASIC.

    摘要翻译: 提供了包覆成型的压力传感器封装。 压力传感器模具(Pcell)被封盖,使得Pcell具有增强的刚度以承受由模制密封剂产生的应力效应。 Pcell帽包括一个远离Pcell隔膜的孔,使得Pcell能够承受外部气体压力,同时将水分从隔膜引导出来。 凝胶不需要使用,相反,如果需要,可以在Pcell上沉积软膜以保护Pcell隔膜免受过多的水分。 Pcell帽可以采取例如虚拟硅晶片或功能ASIC的形式。

    Methods and apparatus for a Quad Flat No-Lead (QFN) package
    34.
    发明申请
    Methods and apparatus for a Quad Flat No-Lead (QFN) package 有权
    四方扁平无引线(QFN)封装的方法和装置

    公开(公告)号:US20080099899A1

    公开(公告)日:2008-05-01

    申请号:US11590327

    申请日:2006-10-31

    IPC分类号: H01L23/02

    摘要: Methods and apparatus are provided for decreasing the size of Quad Flat No-Lead (QFN) packages (300, 400) down to chip-scale packages. Such QFN packages include a first semiconductor chip (310, 410), a plurality of recessed leads (306, 406, 408, 411) having mold lock features, and a mold material 340, 440 substantially encasing all sides of the semiconductor chip. An active surface (314, 414) of the semiconductor chip is oriented toward a mounting side (307, 407) of the QFN package, and a plurality of wire bonds 330, 430 disposed between the active surface and the mounting side couple the active side to the leads. The QFN packages may also include a second semiconductor chip (452) coupled to a plurality of leads (408) and to the first semiconductor chip via wire bonds (431, 432) in a manner similar to the first semiconductor chip.

    摘要翻译: 提供了将Quad Flat No-Lead(QFN)封装(300,400)的尺寸缩小到芯片级封装的方法和装置。 这种QFN封装包括第一半导体芯片(310,410),具有模具锁定特征的多个凹陷引线(306,406,408,411)以及基本上封装半导体芯片的所有侧面的模具材料340,440。 半导体芯片的有源表面(314,414)朝向QFN封装的安装侧(307,407)取向,并且设置在有源表面和安装侧之间的多个引线接合330,430将活动侧 到线索 QFN封装还可以包括以类似于第一半导体芯片的方式通过引线键合(431,432)耦合到多个引线(408)的第二半导体芯片(452)和第一半导体芯片(431)。