公开(公告)号：US06169771A

公开(公告)日：2001-01-02

申请号：US09014264

申请日：1998-01-27

申请人： Guoliang Shou ,  Changming Zhou ,  Xuping Zhou ,  Xiaoling Oin ,  Kazunori Motohashi ,  Makoto Yamamoto ,  Sunao Takatori

发明人： Guoliang Shou ,  Changming Zhou ,  Xuping Zhou ,  Xiaoling Oin ,  Kazunori Motohashi ,  Makoto Yamamoto ,  Sunao Takatori

IPC分类号： H04L2706

CPC分类号： H03H17/0254 ,  H04B1/7093

摘要： In one aspect, the present invention provides a low power consumption matched filter. The signal received at an input terminal is input to a shift register having stages equal to the spread code length number after conversion into digital signals in an A/D converter. The outputs of the shift register stages are input to XOR circuits set corresponding to each stage, so that XOR operations are performed between the outputs and corresponding spread code bits d1 to dN. The outputs of the XOR circuits are analogously added in an analog adder and output from an output terminal. In another aspect, a filter circuit uses an analog operation circuit to prevent lowered operational accuracy caused by residual charge. Input analog signals successively undergo sampling and holding in sample-and-hold circuits, are multiplied by coefficients stored in a shift register by multiplication circuits, and added in an addition circuit. Sample data transmission error storage is prevented by shifting coefficients in the shift register. Sample-and-hold circuits and multiplication circuits are formed by analog operation circuits, and each include a switch for canceling the residual charge. The sample-and-hold circuits and multiplication circuits normally working are refreshed sequentially by providing circuits for replacing their function. The addition circuit is refreshed in the same way.

摘要翻译： 一方面，本发明提供一种低功耗匹配滤波器。 在A / D转换器转换成数字信号之后，在输入端接收的信号被输入到具有等于扩展码长度数的级的移位寄存器。 移位寄存器级的输出被输入到对应于每一级的XOR电路，从而在输出和对应的扩展码位d1至dN之间执行异或运算。 XOR电路的输出类似地添加到模拟加法器中并从输出端子输出。 另一方面，滤波器电路使用模拟运算电路来防止由剩余电荷引起的运算精度降低。 输入模拟信号在采样保持电路中连续进行采样和保持，乘以乘法电路存储在移位寄存器中的系数，并加入加法电路。 通过移位寄存器中的系数来防止采样数据传输错误存储。 采样保持电路和乘法电路由模拟操作电路形成，并且每个都包括用于消除剩余电荷的开关。 正常工作的采样保持电路和乘法电路通过提供更换其功能的电路依次刷新。 加法电路以相同的方式刷新。

公开(公告)号：US06031415A

公开(公告)日：2000-02-29

申请号：US733820

申请日：1996-10-18

申请人： Guoliang Shou ,  Changming Zhou ,  Makoto Yamamoto ,  Mamoru Sawahashi ,  Fumiyuki Adachi ,  Sunao Takatori

发明人： Guoliang Shou ,  Changming Zhou ,  Makoto Yamamoto ,  Mamoru Sawahashi ,  Fumiyuki Adachi ,  Sunao Takatori

IPC分类号： H04J13/00 ,  H03H17/02 ,  H04B1/7093 ,  H03K5/00 ,  H03D1/00

CPC分类号： H03H17/0254 ,  H04B1/707

摘要： The present invention provides a matched filter circuit available for processing long P/N codes in a small size circuit. A matched filter circuit according to the present invention performs the following processes in the proposed invention: i) sampling and holding circuits multiply part of the number of a long code; ii) multipliers are input in parallel to the sampling and holding circuit from the first multiplier register which can hold as many PN codes as the number of the sampling and holding circuits in i); iii) the PN codes are stored in the second multiplier register of the same capacity of the first multiplier resister when there is a PN code to be used sequentially to be PN codes; and iv) the PN codes in the second multiplier register are transmitted in parallel to the first multiplier register. The PN code is input to the second multiplier register in serial.

摘要翻译： 本发明提供了可用于处理小尺寸电路中的长P / N码的匹配滤波器电路。 根据本发明的匹配滤波器电路在所提出的发明中执行以下处理：i）采样和保持电路乘以长码的数量的一部分; ii）乘法器与来自第一乘法器寄存器的采样和保持电路并联输入，其可以容纳与i）中的采样和保持电路的数量一样多的PN码; iii）当存在要被顺序使用的PN码为PN码时，PN码存储在第一乘法器电阻相同容量的第二乘法器寄存器中; 和iv）第二乘法器寄存器中的PN码并行发送到第一乘法器寄存器。 PN码以串行方式输入到第二个乘法器寄存器。

公开(公告)号：US5926512A

公开(公告)日：1999-07-20

申请号：US735787

申请日：1996-10-23

申请人： Guoliang Shou ,  Changming Zhou ,  Makoto Yamamoto ,  Sunao Takatori ,  Mamoru Sawahashi ,  Fumiyuki Adachi

发明人： Guoliang Shou ,  Changming Zhou ,  Makoto Yamamoto ,  Sunao Takatori ,  Mamoru Sawahashi ,  Fumiyuki Adachi

IPC分类号： H04J13/00 ,  H03H11/04 ,  H03H17/02 ,  H03H19/00 ,  H04B1/7093 ,  H03D1/00 ,  H04L27/06

CPC分类号： H03H11/04 ,  H03H17/0254 ,  Y02B60/50

摘要： A matched filter circuit for mobile communications is disclosed. The circuit may be fabricated in a small size using large-scale integration and can perform high-speed processing and double sampling at a reduced rate of power consumption. In one embodiment, a plurality of sampling and holding circuits each including a switch are divided into two groups. A control circuit successively closes one of the switches in the first group every chip time, while successively closing one of the switches in the second group at a timing shifted by one-half chip time from that of the first group, thereby enabling a double-sampling operation. Outputs of the sampling and holding circuits in each group are summed by an analog circuit with a high degree of linearity, resulting in a high processing speed combined with a reduced circuit size and power consumption.

摘要翻译： 公开了一种用于移动通信的匹配滤波器电路。 该电路可以使用大规模集成在小尺寸上制造，并且可以以降低的功率消耗来执行高速处理和双重采样。 在一个实施例中，每个包括开关的多个采样和保持电路被分成两组。 控制电路在每个码片时间连续地闭合第一组中的一个开关，同时以与第一组相比半个码片时间偏移的时间顺序地关闭第二组中的一个开关，由此， 抽样操作。 每个组中的采样和保持电路的输出由具有高线性度的模拟电路相加，导致高处理速度以及减小的电路尺寸和功耗。

公开(公告)号：US5910948A

公开(公告)日：1999-06-08

申请号：US955613

申请日：1997-10-22

申请人： Guoliang Shou ,  Changming Zhou ,  Xuping Zhou ,  Makoto Yamamoto ,  Sunao Takatori ,  Mamoru Sawahashi ,  Fumiyuki Adachi

发明人： Guoliang Shou ,  Changming Zhou ,  Xuping Zhou ,  Makoto Yamamoto ,  Sunao Takatori ,  Mamoru Sawahashi ,  Fumiyuki Adachi

IPC分类号： H04B1/707 ,  H04B1/708 ,  H04B1/7083 ,  H04B7/26 ,  H04J13/00 ,  H04L7/00 ,  H04W36/00 ,  H04W48/18 ,  H04W56/00 ,  H04B7/216

CPC分类号： H04W48/18 ,  H04B1/70735 ,  H04B1/70775 ,  H04B1/708 ,  H04B1/7083 ,  H04B1/7093 ,  H04B1/7117 ,  H04B2201/70702 ,  H04W36/00

摘要： The present invention realizes a rapid and efficient cell search and small-size instrument for an asynchronous DS-CDMA cellular system. This cell search detects the correlation between the received signal and the short code of the control channel, and matched filter 22 detects the maximum electric power correlation peak location. Next, using correlators 28-1 to 28-n which are parallelly set in a plurality for RAKE processing with plurality, identifies the long code that is set in the system with the detected long code timing. After the long code is synchronized, a multipath signal is received using 28-1 to 28-n, and the data is judged by RAKE processing. When peripheral cell search is executed, after long code timing is detected by using matched filter 22, the long code of the candidate peripheral cell is designated using the same matched filter. Handover is safely realized by receiving the signal from the connected base station by correlators 28-1 to 28-n, and the base station signal through handover by 22.

摘要翻译： 本发明实现了用于异步DS-CDMA蜂窝系统的快速且有效的小区搜索和小尺寸仪器。 该小区搜索检测接收信号与控制信道的短码之间的相关性，匹配滤波器22检测最大功率相关峰位置。 接下来，使用多个并行设置为用于RAKE处理的多个的相关器28-1至28-n识别具有检测到的长码定时的系统中设置的长码。 在长代码同步之后，使用28-1至28-n接收多路径信号，并且通过RAKE处理来判断数据。 当执行外围小区搜索时，在通过使用匹配滤波器22检测长码定时之后，使用相同的匹配滤波器来指定候选周边小区的长码。 通过由相关器28-1至28-n接收来自所连接的基站的信号，以及通过22次切换的基站信号来安全地实现切换。

公开(公告)号：US5790590A

公开(公告)日：1998-08-04

申请号：US740672

申请日：1996-10-31

申请人： Guoliang Shou ,  Changming Zhou ,  Makoto Yamamoto ,  Sunao Takatori ,  Mamoru Sawahashi ,  Fumiyuki Adachi

发明人： Guoliang Shou ,  Changming Zhou ,  Makoto Yamamoto ,  Sunao Takatori ,  Mamoru Sawahashi ,  Fumiyuki Adachi

IPC分类号： H03H15/00 ,  H03H17/02 ,  H04B1/7093 ,  H04J13/00 ,  H04B15/00

CPC分类号： H04B1/7093

摘要： The present invention has an object to provide a matched filter circuit which is possible to synchronize a spreading code with an input signal. A matched filter according to the present invention samples input signal in response to three clocks from the first to the third shifted by a half cycle of a sampling signal so as to judge whether the sampling clock is ahead or behind of the input signal according to signs of input signal sampled. One clock is selected to be the sampling clock.

摘要翻译： 本发明的目的是提供一种可以使扩展码与输入信号同步的匹配滤波器电路。 根据本发明的匹配滤波器响应于从第一到第三的三个时钟采样输入信号，移位了采样信号的半个周期，以便根据符号判断采样时钟是否在输入信号的前面或后面 的输入信号采样。 选择一个时钟作为采样时钟。

公开(公告)号：US5774008A

公开(公告)日：1998-06-30

申请号：US766875

申请日：1996-12-13

申请人： Guoliang Shou ,  Sunao Takatori ,  Makoto Yamamoto

发明人： Guoliang Shou ,  Sunao Takatori ,  Makoto Yamamoto

IPC分类号： G06G7/06 ,  G06G7/14 ,  G06G7/26 ,  G06J1/00 ,  G06N3/063 ,  G11C27/02 ,  G06G7/42 ,  H03K17/62

CPC分类号： G11C27/024 ,  G06G7/06 ,  G06G7/14 ,  G06G7/26 ,  G06J1/00 ,  G06N3/0635

摘要： Addition is performed by a capacitive coupling or resistive coupling. A quantizing circuit is realized by plurality of thresholding circuits receiving an analog input voltages. Subtraction in performed by two MOSs of anti-polarity inputted analog input voltages to gates.

摘要翻译： 通过电容耦合或电阻耦合进行加法。 量化电路由接收模拟输入电压的多个阈值电路实现。 由两个MOS反极性输入的模拟输入电压对门进行减法。

公开(公告)号：US5748510A

公开(公告)日：1998-05-05

申请号：US536244

申请日：1995-09-29

申请人： Guoliang Shou ,  Kazunori Motohashi ,  Makoto Yamamoto ,  Sunao Takatori

发明人： Guoliang Shou ,  Kazunori Motohashi ,  Makoto Yamamoto ,  Sunao Takatori

IPC分类号： G06G7/16 ,  G06J1/00

CPC分类号： G06J1/00

摘要： A multiplication circuit includes a plurality of switches which receive a common analog input voltage and a reference voltage and which alternatively output the input voltage or the reference voltage. A first capacitive coupling is provided which has a plurality of capacitors, each of which receives an output from a respective switch, and a second capacitive coupling is provided with a plurality of capacitors, each of which likewise receives an output from a respective switch. One or more of the capacitors in the first capacitive coupling is connected to the second capacitive coupling. A first inverted amplifier and a second inverted amplifier are connected in series to the output of the second capacitive coupling with individual feedback.

摘要翻译： 乘法电路包括多个开关，其接收公共模拟输入电压和参考电压，并且输出输入电压或参考电压。 提供了第一电容耦合，其具有多个电容器，每个电容器接收来自相应开关的输出，并且第二电容耦合提供有多个电容器，每个电容器同样接收来自相应开关的输出。 第一电容耦合中的一个或多个电容器连接到第二电容耦合。 第一反相放大器和第二反相放大器与具有各个反馈的第二电容耦合的输出串联连接。

公开(公告)号：US5737368A

公开(公告)日：1998-04-07

申请号：US715321

申请日：1996-09-17

申请人： Guoliang Shou ,  Changming Zhou ,  Makoto Yamamoto ,  Sunao Takatori

发明人： Guoliang Shou ,  Changming Zhou ,  Makoto Yamamoto ,  Sunao Takatori

IPC分类号： H04J13/00 ,  G11C27/02 ,  H03H11/04 ,  H03H17/02 ,  H04B1/7093 ,  H03D1/00

CPC分类号： H03H11/04 ,  H03H17/0254

摘要： A matched filter contains a plurality of auxiliary sampling and holding circuits in addition to a main sampling and holding circuit containing multiple unit sampling and holding circuits. An auxiliary sampling and holding circuit is used to hold an input voltage, which would ordinarily be held by a unit sampling and holding circuit, when the unit sampling and holding circuit is being refreshed. By holding a part of the analog input voltage in the auxiliary sampling and holding circuits, refreshing is performed without decreasing the overall calculation speed.

摘要翻译： 除了包含多个单元采样和保持电路的主采样和保持电路之外，匹配滤波器还包含多个辅助采样和保持电路。 当单元采样和保持电路被刷新时，辅助采样和保持电路用于保持通常由单元采样和保持电路保持的输入电压。 通过将模拟输入电压的一部分保持在辅助采样和保持电路中，在不降低总体计算速度的情况下执行刷新。

公开(公告)号：US5708384A

公开(公告)日：1998-01-13

申请号：US650909

申请日：1996-05-17

申请人： Guoliang Shou ,  Sunao Takatori ,  Makoto Yamamoto

发明人： Guoliang Shou ,  Sunao Takatori ,  Makoto Yamamoto

IPC分类号： G06J1/00 ,  G11C27/02 ,  H03K19/0175 ,  G06G7/16

CPC分类号： G06J1/00 ,  G11C27/026

摘要： A computational circuit which has a capacitive coupling for weighted addition. Addition is performed by the capacitive coupling. By connecting and disconnecting capacitances of the capacitive coupling, multiplication can be executed by changing the weights of the capacitors. An inverter with a feed back capacitance is connected to a computational circuit to improve the accuracy of the computation. Capacitances consist of unit capacitances of scattered distribution, so that the deviation of the capacities is minimized.

摘要翻译： 具有用于加权相加的电容耦合的计算电路。 通过电容耦合进行加法。 通过连接和断开电容耦合的电容，可以通过改变电容器的重量来执行相乘。 具有反馈电容的逆变器连接到计算电路以提高计算的精度。 电容由分散分布的单位电容组成，使容量的偏差最小化。

公开(公告)号：US5563812A

公开(公告)日：1996-10-08

申请号：US377041

申请日：1995-01-23

申请人： Guoliang Shou ,  Sunao Takatori ,  Makoto Yamamoto

发明人： Guoliang Shou ,  Sunao Takatori ,  Makoto Yamamoto

IPC分类号： H03H15/00 ,  H03H17/02 ,  G06J1/00

CPC分类号： H03H17/0291 ,  H03H15/00

摘要： A filter circuit switches a switching mechanism based on multipliers held in a data register DATA RGST as a digital data. Based on the output data of data register DATA RGST, a multiplication circuit M is arranged to have weights corresponding to a capacity of capacitance connected with a common analog input voltage X.

摘要翻译： 滤波器电路基于保持在数据寄存器DATA RGST中的乘法器作为数字数据切换开关机构。 基于数据寄存器DATA RGST的输出数据，乘法电路M被配置为具有对应于与公共模拟输入电压X连接的电容容量的权重。