公开(公告)号：US20190074350A1

公开(公告)日：2019-03-07

申请号：US16178065

申请日：2018-11-01

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey Alan West ,  Thomas D. Bonifield ,  Byron Lovell Williams

IPC: H01L49/02 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L23/522 ,  H01L21/8234 ,  H01L27/06

CPC classification number: H01L28/91 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/823481 ,  H01L23/522 ,  H01L23/5225 ,  H01L27/0629 ,  H01L28/00 ,  H01L28/40 ,  H01L28/60 ,  H01L29/0692 ,  H01L29/66477 ,  H01L29/78 ,  H01L29/7833

Abstract: A microelectronic device contains a high voltage component having a high voltage node and a low voltage node. The high voltage node is isolated from the low voltage node by a main dielectric between the high voltage node and low voltage elements at a surface of the substrate of the microelectronic device. A lower-bandgap dielectric layer is disposed between the high voltage node and the main dielectric. The lower-bandgap dielectric layer contains at least one sub-layer with a bandgap energy less than a bandgap energy of the main dielectric. The lower-bandgap dielectric layer extends beyond the high voltage node continuously around the high voltage node. The lower-bandgap dielectric layer has an isolation break surrounding the high voltage node at a distance of at least twice the thickness of the lower-bandgap dielectric layer from the high voltage node.

公开(公告)号：US09768245B2

公开(公告)日：2017-09-19

申请号：US15045449

申请日：2016-02-17

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey Alan West ,  Thomas D. Bonifield ,  Byron Lovell Williams

IPC: H01L49/02 ,  H01L21/02 ,  H01L29/78 ,  H01L27/06 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L28/91 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/823481 ,  H01L27/0629 ,  H01L28/40 ,  H01L28/60 ,  H01L29/0692 ,  H01L29/66477 ,  H01L29/78 ,  H01L29/7833

Abstract: A microelectronic device contains a high voltage component having a high voltage node and a low voltage node. The high voltage node is isolated from the low voltage node by a main dielectric between the high voltage node and low voltage elements at a surface of the substrate of the microelectronic device. A lower-bandgap dielectric layer is disposed between the high voltage node and the main dielectric. The lower-bandgap dielectric layer contains at least one sub-layer with a bandgap energy less than a bandgap energy of the main dielectric. The lower-bandgap dielectric layer extends beyond the high voltage node continuously around the high voltage node. The lower-bandgap dielectric layer has an isolation break surrounding the high voltage node at a distance of at least twice the thickness of the lower-bandgap dielectric layer from the high voltage node.

公开(公告)号：US09741787B2

公开(公告)日：2017-08-22

申请号：US15348698

申请日：2016-11-10

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey Alan West ,  Thomas D. Bonifield ,  Byron Lovell Williams

IPC: H01L49/02

CPC classification number: H01L28/60 ,  H01L23/5223 ,  H01L23/552 ,  H01L23/642 ,  H01L28/40

Abstract: High voltage integrated circuit capacitors are disclosed. In an example arrangement. A capacitor structure includes a semiconductor substrate; a bottom plate having a conductive layer overlying the semiconductor substrate; a capacitor dielectric layer deposited overlying at least a portion of the bottom plate and having a first thickness greater than about 6 um in a first region; a sloped transition region in the capacitor dielectric at an edge of the first region, the sloped transition region having an upper surface with a slope of greater than 5 degrees from a horizontal plane and extending from the first region to a second region of the capacitor dielectric layer having a second thickness lower than the first thickness; and a top plate conductor formed overlying at least a portion of the capacitor dielectric layer in the first region. Methods and additional apparatus arrangements are disclosed.

公开(公告)号：US09525021B2

公开(公告)日：2016-12-20

申请号：US14933638

申请日：2015-11-05

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey Alan West ,  Thomas D. Bonifield ,  Byron Lovell Williams

IPC: H01L49/02

CPC classification number: H01L28/60 ,  H01L23/5223 ,  H01L23/552 ,  H01L23/642 ,  H01L28/40

Abstract: High voltage integrated circuit capacitors are disclosed. In an example arrangement, A capacitor structure includes a semiconductor substrate; a bottom plate having a conductive layer overlying the semiconductor substrate; a capacitor dielectric layer deposited overlying at least a portion of the bottom plate and having a first thickness greater than about 6 um in a first region; a sloped transition region in the capacitor dielectric at an edge of the first region, the sloped transition region having an upper surface with a slope of greater than 5 degrees from a horizontal plane and extending from the first region to a second region of the capacitor dielectric layer having a second thickness lower than the first thickness; and a top plate conductor formed overlying at least a portion of the capacitor dielectric layer in the first region. Methods and additional apparatus arrangements are disclosed.

Abstract translation: 公开了高压集成电路电容器。 在示例性布置中，A电容器结构包括半导体衬底; 底板，其具有覆盖在半导体衬底上的导电层; 沉积在所述底板的至少一部分上并且在第一区域中具有大于约6um的第一厚度的电容器电介质层; 在第一区域的边缘处的电容器电介质中的倾斜过渡区域，所述倾斜过渡区域具有从水平面倾斜大于5度的上表面并从电容器电介质的第一区域延伸到第二区域 层，其具有比第一厚度低的第二厚度; 以及形成在所述第一区域中覆盖所述电容器电介质层的至少一部分的顶板导体。 公开了方法和附加装置布置。

公开(公告)号：US20160133690A1

公开(公告)日：2016-05-12

申请号：US14933638

申请日：2015-11-05

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey Alan West ,  Thomas D. Bonifield ,  Byron Lovell Williams

IPC: H01L49/02

CPC classification number: H01L28/60 ,  H01L23/5223 ,  H01L23/552 ,  H01L23/642 ,  H01L28/40

Abstract: High voltage integrated circuit capacitors are disclosed. In an example arrangement, A capacitor structure includes a semiconductor substrate; a bottom plate having a conductive layer overlying the semiconductor substrate; a capacitor dielectric layer deposited overlying at least a portion of the bottom plate and having a first thickness greater than about 6 um in a first region; a sloped transition region in the capacitor dielectric at an edge of the first region, the sloped transition region having an upper surface with a slope of greater than 5 degrees from a horizontal plane and extending from the first region to a second region of the capacitor dielectric layer having a second thickness lower than the first thickness; and a top plate conductor formed overlying at least a portion of the capacitor dielectric layer in the first region. Methods and additional apparatus arrangements are disclosed.

Abstract translation: 公开了高压集成电路电容器。 在示例性布置中，A电容器结构包括半导体衬底; 底板，其具有覆盖在半导体衬底上的导电层; 沉积在所述底板的至少一部分上并且在第一区域中具有大于约6um的第一厚度的电容器电介质层; 在第一区域的边缘处的电容器电介质中的倾斜过渡区域，所述倾斜过渡区域具有从水平面倾斜大于5度的上表面，并且从第一区域延伸到电容器电介质的第二区域 层，其具有比第一厚度低的第二厚度; 以及形成在所述第一区域中覆盖所述电容器电介质层的至少一部分的顶板导体。 公开了方法和附加装置布置。

公开(公告)号：US20160133580A1

公开(公告)日：2016-05-12

申请号：US14854896

申请日：2015-09-15

Applicant: Texas Instruments Incorporated

Inventor： Thomas D. Bonifield ,  Jeffrey A. West ,  Byron Williams ,  Honglin Guo

IPC: H01L23/00 ,  H01L23/58

CPC classification number: H01L23/562 ,  H01L23/3171 ,  H01L23/585 ,  H01L23/62 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2924/00014 ,  H01L2924/3862 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/4554

Abstract: A semiconductor die includes a plurality of layers, the plurality of layers having a top surface. A scribe seal is located in the plurality of layers and includes a first metal stack having a first metal layer located proximate the top surface. A trench is located in at least one layer of the plurality of layers. The trench extends from the top surface of the plurality of layers and is located a distance from the first metal stack. An electrical insulating layer is located on the top surface. The electrical insulating layer covers at least a portion of the top surface adjacent the first metal layer and extends a distance from the top surface of the first metal layer.

Abstract translation: 半导体管芯包括多个层，所述多个层具有顶表面。 划片密封件位于多个层中，并且包括具有位于顶表面附近的第一金属层的第一金属堆叠。 沟槽位于多层中的至少一层中。 沟槽从多个层的顶表面延伸并且距离第一金属叠层一定距离。 电绝缘层位于顶表面上。 电绝缘层覆盖与第一金属层相邻的顶表面的至少一部分，并从第一金属层的顶表面延伸一段距离。