公开(公告)号：US20160365447A1

公开(公告)日：2016-12-15

申请号：US15247024

申请日：2016-08-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhiqiang Wu ,  Yi-Ming Sheu ,  Tzer-Min Shen ,  Chun-Fu Cheng ,  Hong-Shen Chen

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08

CPC classification number: H01L29/7848 ,  H01L21/26586 ,  H01L29/0615 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66598 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/785 ,  H01L29/7851

Abstract: The demand for increased performance and shrinking geometry from ICs has brought the introduction of multi-gate devices including finFET devices. Inducing a higher tensile strain/stress in a region provides for enhanced electron mobility, which may improve performance. High temperature processes during device fabrication tend to relax the stress on these strain inducing layers. The present disclosure relates to a method of forming a strain inducing layer or cap layer at the RPG (replacement poly silicon gate) stage of a finFET device formation process. In some embodiments, the strain inducing layer is doped to reduce the external resistance.

Abstract translation: IC的性能提升和几何尺寸的需求引起了包括finFET器件在内的多栅极器件的引入。 在区域中诱导更高的拉伸应变/应力提供增强的电子迁移率，这可以提高性能。 器件制造期间的高温工艺往往会使这些应变诱导层的应力松弛。 本公开涉及在finFET器件形成工艺的RPG（替代多晶硅栅极）级形成应变诱导层或覆盖层的方法。 在一些实施例中，应变诱导层被掺杂以减小外部电阻。