公开(公告)号：US09455346B2

公开(公告)日：2016-09-27

申请号：US14100263

申请日：2013-12-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhiqiang Wu ,  Yi-Ming Sheu ,  Tzer-Min Shen ,  Chun-Fu Cheng ,  Hong-Shen Chen

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/7848 ,  H01L21/26586 ,  H01L29/0615 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66598 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/785 ,  H01L29/7851

Abstract: The demand for increased performance and shrinking geometry from ICs has brought the introduction of multi-gate devices including finFET devices. Inducing a higher tensile strain/stress in a region provides for enhanced electron mobility, which may improve performance. High temperature processes during device fabrication tend to relax the stress on these strain inducing layers. The present disclosure relates to a method of forming a strain inducing layer or cap layer at the RPG (replacement poly silicon gate) stage of a finFET device formation process. In some embodiments, the strain inducing layer is doped to reduce the external resistance.

Abstract translation: IC的性能提升和几何尺寸的需求引起了包括finFET器件在内的多栅极器件的引入。 在区域中诱导更高的拉伸应变/应力提供增强的电子迁移率，这可以提高性能。 器件制造期间的高温工艺往往会使这些应变诱导层的应力松弛。 本公开涉及在finFET器件形成工艺的RPG（替代多晶硅栅极）级形成应变诱导层或覆盖层的方法。 在一些实施例中，应变诱导层被掺杂以减小外部电阻。

公开(公告)号：US20160035892A1

公开(公告)日：2016-02-04

申请号：US14880392

申请日：2015-10-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Hsing Yu ,  Shih-Syuan Huang ,  Yi-Ming Sheu ,  Ken-Ichi Goto

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/417 ,  H01L29/16 ,  H01L29/167

CPC classification number: H01L29/7847 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/26593 ,  H01L29/0603 ,  H01L29/1083 ,  H01L29/1608 ,  H01L29/167 ,  H01L29/24 ,  H01L29/41766 ,  H01L29/42364 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7848

Abstract: The present disclosure relates to method of forming a transistor device having epitaxial source and drain regions with dislocation stress memorization (DSM) regions that provide stress to an epitaxial channel region, and an associated device. The method forms a first dislocation stress memorization (DSM) region and a second DSM region having stressed lattices within a substrate. The substrate is selectively etched to form a source cavity and a drain cavity extending from an upper surface of the substrate to positions contacting the first DSM region and the second DSM region. An epitaxial source is formed within the source cavity and an epitaxial drain region is formed within the drain cavity. A gate structure is formed over the substrate at a location laterally between the epitaxial source region and the epitaxial drain region.

Abstract translation: 本公开涉及形成具有外延源极和漏极区域的晶体管器件的方法，该区域具有向外延沟道区域提供应力的位错应力存储（DSM）区域以及相关联的器件。 该方法形成第一位错应力记忆（DSM）区域和在衬底内具有受压晶格的第二DSM区域。 选择性地蚀刻衬底以形成从衬底的上表面延伸到与第一DSM区和第二DSM区接触的位置的源腔和漏腔。 在源极腔内形成外延源，在漏极腔内形成外延漏极区。 在外延源极区域和外延漏极区域之间的横向位置的衬底上形成栅极结构。

公开(公告)号：US09252236B2

公开(公告)日：2016-02-02

申请号：US14222759

申请日：2014-03-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Syuan Huang ,  Tsung-Hsing Yu ,  Yi-Ming Sheu

IPC: H01L21/265 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/66492 ,  H01L21/26586 ,  H01L29/1041 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method for improving analog gain in long channel devices associated with a semiconductor workpiece is provided. A gate oxide layer is formed on the semiconductor workpiece, and a plurality of gate structures are formed over the gate oxide layer, wherein a first pair of the plurality of gate structures define a short channel device region and a second pair of the plurality of gate structures define a long channel device region. A first ion implantation with a first dopant is performed at a first angle, wherein the first dopant is one of an n-type dopant and a p-type dopant. A second ion implantation with a second dopant is performed at a second angle, wherein the second angle is greater than the first angle. The second dopant is one or an n-type dopant and a p-type dopant that is opposite of the first dopant, and a height of the plurality of gate structures and the second angle generally prevents the second ion implantation from implanting ions into the short channel device region.

Abstract translation: 提供了一种用于改善与半导体工件相关联的长通道器件中的模拟增益的方法。 在半导体工件上形成栅极氧化层，并且在栅极氧化物层上形成多个栅极结构，其中多个栅极结构中的第一对限定短沟道器件区域和第二对多个栅极 结构定义了一个长通道器件区域。 以第一角度执行具有第一掺杂剂的第一离子注入，其中第一掺杂剂是n型掺杂剂和p型掺杂剂之一。 以第二角度执行具有第二掺杂剂的第二离子注入，其中第二角度大于第一角度。 第二掺杂剂是与第一掺杂剂相反的一种或n型掺杂剂和p型掺杂剂，并且多个栅极结构的高度和第二角度通常防止第二离子注入将离子注入到短路中 通道设备区域。

公开(公告)号：US10008603B2

公开(公告)日：2018-06-26

申请号：US15355844

申请日：2016-11-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Sheng Wei ,  Hung-Li Chiang ,  Chia-Wen Liu ,  Yi-Ming Sheu ,  Zhiqiang Wu ,  Chung-Cheng Wu ,  Ying-Keung Leung

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/165 ,  H01L21/02 ,  H01L21/311 ,  H01L21/306 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/7851 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/31111 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/78654 ,  H01L29/78696

Abstract: A method of fabrication of a multi-gate semiconductor device that includes providing a fin having a plurality of a first type of epitaxial layers and a plurality of a second type of epitaxial layers. A first portion of a first layer of the second type of epitaxial layers is removed in a channel region of the fin to form an opening between a first layer of the first type of epitaxial layer and a second layer of the first type of epitaxial layer. A portion of a gate structure is then formed having a gate dielectric and a gate electrode in the opening. A dielectric material is formed abutting the portion of the gate structure.

公开(公告)号：US09899475B2

公开(公告)日：2018-02-20

申请号：US15172417

申请日：2016-06-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Hsing Yu ,  Shih-Syuan Huang ,  Ken-Ichi Goto ,  Yi-Ming Sheu

IPC: H01L29/10 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/165 ,  H01L29/78 ,  H01L29/66 ,  H01L21/265

CPC classification number: H01L29/1054 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823425 ,  H01L27/088 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66492 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present disclosure relate to an integrated chip having long-channel and short-channel transistors having channel regions with different doping profiles. In some embodiments, the integrated chip includes a first gate electrode arranged over a first channel region having first length, and a second gate electrode arranged over a second channel region having a second length greater than the first length. The first channel region and the second channel region have a dopant profile, respectively along the first length and the second length, which has a dopant concentration that is higher by edges than in a middle of the first channel region and the second channel region. The dopant concentration is also higher by the edges of the first channel region than by the edges of the second channel region.

公开(公告)号：US20170054022A1

公开(公告)日：2017-02-23

申请号：US15345814

申请日：2016-11-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Hsing Yu ,  Shih-Syuan Huang ,  Yi-Ming Sheu ,  Ken-Ichi Goto

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L29/167 ,  H01L29/417 ,  H01L21/265 ,  H01L29/16

CPC classification number: H01L29/7847 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/26593 ,  H01L29/0603 ,  H01L29/1083 ,  H01L29/1608 ,  H01L29/167 ,  H01L29/24 ,  H01L29/41766 ,  H01L29/42364 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7848

Abstract: The present disclosure relates to a transistor device having epitaxial source and drain regions with dislocation stress memorization (DSM) regions that provide stress to a channel region. In some embodiments, the transistor device has an epitaxial source region arranged within a substrate. An epitaxial drain region is arranged within the substrate and is separated from the epitaxial source region by a channel region. A first DSM region, which has a stressed lattice configured to generate stress within the channel region, extends from below the epitaxial source region to a location within the epitaxial source region. A second DSM region, which has a stressed lattice configured to generate stress within the channel region, extends from below the epitaxial drain region to a location within the epitaxial drain region.

Abstract translation: 本公开涉及具有外延源极和漏极区域的晶体管器件，其具有向沟道区域提供应力的位错应力记忆（DSM）区域。 在一些实施例中，晶体管器件具有布置在衬底内的外延源极区域。 外延漏极区域布置在衬底内并且通过沟道区域与外延源极区域分离。 具有被配置为在沟道区内产生应力的受应力晶格的第一DSM区从外延源区的下方延伸到外延源区内的位置。 具有被配置为在沟道区内产生应力的应力晶格的第二DSM区从外延漏极区的下方延伸到外延漏极区内的位置。

公开(公告)号：US09502409B2

公开(公告)日：2016-11-22

申请号：US14624782

申请日：2015-02-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jon-Hsu Ho ,  Chih-Ching Wang ,  Ching-Fang Huang ,  Wen-Hsing Hsieh ,  Tsung-Hsing Yu ,  Yi-Ming Sheu ,  Chih Chieh Yeh ,  Ken-Ichi Goto ,  Zhiqiang Wu

IPC: H01L29/78 ,  H01L27/088 ,  H01L27/092 ,  H01L29/10

CPC classification number: H01L27/0886 ,  H01L27/0924 ,  H01L29/105 ,  H01L29/7831 ,  H01L29/7833 ,  H01L29/785 ,  H01L29/7851

Abstract: A multi-gate semiconductor device is formed including a semiconductor substrate. The multi-gate semiconductor device also includes a first transistor including a first fin portion extending above the semiconductor substrate. The first transistor has a first channel region formed therein. The first channel region includes a first channel region portion doped at a first concentration of a first dopant type and a second channel region portion doped at a second concentration of the first dopant type. The second concentration is higher than the first concentration. The first transistor further includes a first gate electrode layer formed over the first channel region. The first gate electrode layer may be of a second dopant type. The first dopant type may be N-type and the second dopant type may be P-type. The second channel region portion may be formed over the first channel region portion.

公开(公告)号：US10861972B2

公开(公告)日：2020-12-08

申请号：US16390373

申请日：2019-04-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhiqiang Wu ,  Yi-Ming Sheu ,  Tzer-Min Shen ,  Chun-Fu Cheng ,  Hong-Shen Chen

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L29/66 ,  H01L29/10 ,  H01L21/265

Abstract: The demand for increased performance and shrinking geometry from ICs has brought the introduction of multi-gate devices including finFET devices. Inducing a higher tensile strain/stress in a region provides for enhanced electron mobility, which may improve performance. High temperature processes during device fabrication tend to relax the stress on these strain inducing layers. In some embodiments, the present disclosure relates to a finFET device and its formation. A strain-inducing layer is disposed on a semiconductor fin between a channel region and a metal gate electrode. First and second inner spacers are disposed on a top surface of the strain-inducing layer and have inner sidewalls disposed along outer sidewalls of the metal gate electrode. First and second outer spacers have innermost sidewalls disposed along outer sidewalls of the first and second inner spacers, respectively. The first and second outer spacers cover outer sidewalls of the first and second inner spacers.

公开(公告)号：US09502559B2

公开(公告)日：2016-11-22

申请号：US14880392

申请日：2015-10-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Hsing Yu ,  Shih-Syuan Huang ,  Yi-Ming Sheu ,  Ken-Ichi Goto

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/167 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/10 ,  H01L21/265

CPC classification number: H01L29/7847 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/26593 ,  H01L29/0603 ,  H01L29/1083 ,  H01L29/1608 ,  H01L29/167 ,  H01L29/24 ,  H01L29/41766 ,  H01L29/42364 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7848

Abstract: The present disclosure relates to method of forming a transistor device having epitaxial source and drain regions with dislocation stress memorization (DSM) regions that provide stress to an epitaxial channel region, and an associated device. The method forms a first dislocation stress memorization (DSM) region and a second DSM region having stressed lattices within a substrate. The substrate is selectively etched to form a source cavity and a drain cavity extending from an upper surface of the substrate to positions contacting the first DSM region and the second DSM region. An epitaxial source is formed within the source cavity and an epitaxial drain region is formed within the drain cavity. A gate structure is formed over the substrate at a location laterally between the epitaxial source region and the epitaxial drain region.

Abstract translation: 本公开涉及形成具有外延源极和漏极区域的晶体管器件的方法，该区域具有向外延沟道区域提供应力的位错应力存储（DSM）区域以及相关联的器件。 该方法形成第一位错应力记忆（DSM）区域和在衬底内具有受压晶格的第二DSM区域。 选择性地蚀刻衬底以形成从衬底的上表面延伸到与第一DSM区和第二DSM区接触的位置的源腔和漏腔。 在源极腔内形成外延源，在漏极腔内形成外延漏极区。 在外延源极区域和外延漏极区域之间的横向位置的衬底上形成栅极结构。

公开(公告)号：US20160284800A1

公开(公告)日：2016-09-29

申请号：US15172417

申请日：2016-06-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Hsing Yu ,  Shih-Syuan Huang ,  Ken-Ichi Goto ,  Yi-Ming Sheu

IPC: H01L29/10 ,  H01L29/78 ,  H01L27/088

CPC classification number: H01L29/1054 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823425 ,  H01L27/088 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66492 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present disclosure relate to an integrated chip having long-channel and short-channel transistors having channel regions with different doping profiles. In some embodiments, the integrated chip includes a first gate electrode arranged over a first channel region having first length, and a second gate electrode arranged over a second channel region having a second length greater than the first length. The first channel region and the second channel region have a dopant profile, respectively along the first length and the second length, which has a dopant concentration that is higher by edges than in a middle of the first channel region and the second channel region. The dopant concentration is also higher by the edges of the first channel region than by the edges of the second channel region.

Abstract translation: 本公开涉及具有具有不同掺杂特性的沟道区的具有长沟道和短沟道晶体管的集成芯片。 在一些实施例中，集成芯片包括布置在具有第一长度的第一沟道区域上的第一栅极电极和布置在具有大于第一长度的第二长度的第二沟道区域上的第二栅电极。 第一沟道区域和第二沟道区域分别具有沿着第一长度和第二长度的掺杂剂分布，其掺杂浓度比边界高于第一沟道区和第二沟道区的中间。 掺杂剂浓度也比第一通道区域的边缘高于第二通道区域的边缘。