公开(公告)号：US09407424B1

公开(公告)日：2016-08-02

申请号：US14682249

申请日：2015-04-09

Applicant: Texas Instruments Incorporated

Inventor： Bharathi Rahuldev Holla ,  Jagdish Chand Goyal ,  Biman Chattopadhyay ,  Sujoy Chakravarty ,  Sumantra Seth

IPC: H04L7/00

CPC classification number: H04L7/0337 ,  H04L7/0004

Abstract: A clock and data recovery module (CDR) is configured to perform fast locking using only two samples per each unit interval (UI). Two clock phase signals are selected from a plurality of clock phase signals. A sequence of data bits is sampled at a rate of two times per UI responsive to the two clock phase signals in which a first sample of each UI is designated as an edge sample a second sample is designated as a data sample. Each edge sample is voted as early/late as compared to an associated data transition of the sequence of data bits by comparing each edge sample to a next data sample. The sample clocks are locked such that edge samples occur in proximity to data transitions by iteratively adjusting a phase of the two selected clock phase signals by a variable step size in response to the early/late vote.

Abstract translation: 时钟和数据恢复模块（CDR）被配置为使用每个单位间隔（UI）仅使用两个采样来执行快速锁定。 从多个时钟相位信号中选择两个时钟相位信号。 响应于两个时钟相位信号，以每个UI两倍的速率对数据比特序列进行采样，其中将每个UI的第一样本指定为边缘样本，将第二样本指定为数据样本。 通过将每个边缘样本与下一个数据样本进行比较，与数据比特序列的相关数据转换相比，每个边缘样本被提前/晚选。 采样时钟被锁定，使得边缘采样在数据转换附近发生，通过响应于早/晚表决反复调整两个所选择的时钟相位信号的相位可变步长。

公开(公告)号：US20160072735A1

公开(公告)日：2016-03-10

申请号：US14850531

申请日：2015-09-10

Applicant: Texas Instruments Incorporated

Inventor： Sumantra Seth ,  Ashwin Ramachandran ,  Gururaj Ghorpade

IPC: H04L12/931 ,  H03F3/45

CPC classification number: H03F1/0277 ,  H03F3/30 ,  H03F3/3032 ,  H03F3/45475 ,  H03F3/72 ,  H03F2200/513 ,  H03F2203/45116 ,  H03F2203/45526

Abstract: Described examples include Ethernet physical layer (PHY) interface integrated circuits with transmit interface circuitry for transmitting data to an Ethernet network through a magnetic interface, which includes a voltage mode first amplifier with an output that generates a first voltage signal from a supply voltage according to a data input signal. The transmit interface circuit also includes a feedforward second amplifier circuit with an output stage that operates in a first mode to generate a current signal from the supply voltage according to the first voltage signal and to provide the current signal to the first amplifier output to boost a peak voltage at the output above the supply voltage to facilitate support for higher peak signal voltage swings for 10Base-T applications while using 2.5 volt or other low voltage supply levels.

Abstract translation: 所描述的实例包括具有发射接口电路的以太网物理层（PHY）接口集成电路，用于通过磁接口将数据发送到以太网络，该磁接口包括电压模式第一放大器，其输出根据电源电压产生第一电压信号 数据输入信号。 发射接口电路还包括前馈第二放大器电路，其具有工作于第一模式的输出级，以根据第一电压信号从电源电压产生电流信号，并将电流信号提供给第一放大器输出以增强 输出高于电源电压的峰值电压，以便于在使用2.5伏或其他低电压电源时支持10Base-T应用的更高峰值信号电压摆幅。

公开(公告)号：US20150115929A1

公开(公告)日：2015-04-30

申请号：US14503545

申请日：2014-10-01

Applicant: Texas Instruments Incorporated

Inventor： Sumantra Seth ,  Subrato Roy ,  Deepak Verma

IPC: G05F5/00 ,  H01C1/16

CPC classification number: G11C5/147 ,  H01C1/16

Abstract: The disclosure provides a voltage regulator for generating piece-wise linear regulated supply voltage. The voltage regulator includes a first clamp circuit that receives a reference voltage and an analog supply voltage. A second clamp circuit receives the reference voltage. A voltage divider circuit is coupled to the first clamp circuit and the second clamp circuit. The voltage divider circuit receives a peripheral supply voltage and generates a regulated supply voltage.

Abstract translation: 本公开提供了用于产生分段线性稳压电源电压的电压调节器。 电压调节器包括接收参考电压和模拟电源电压的第一钳位电路。 第二钳位电路接收参考电压。 分压器电路耦合到第一钳位电路和第二钳位电路。 分压器电路接收外围电源电压并产生稳定的电源电压。