公开(公告)号：US20180247943A1

公开(公告)日：2018-08-30

申请号：US15889182

申请日：2018-02-05

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Wei Feng ,  Shih-Fang Tzou ,  Chien-Ting Ho ,  Ying-Chiao Wang ,  Yu-Ching Chen ,  Hui-Ling Chuang ,  Kuei-Hsuan Yu

IPC: H01L27/108

CPC classification number: H01L27/10855 ,  H01L27/10814 ,  H01L27/10823

Abstract: A semiconductor structure with a capacitor landing pad includes a substrate. A capacitor contact plug is disposed on the substrate. A capacitor landing pad contacts and electrically connects the capacitor contact plug. A bit line is disposed on the substrate. A dielectric layer surrounds the capacitor landing pad. The dielectric layer includes a bottom surface lower than a top surface of the bit line.

公开(公告)号：US20180226408A1

公开(公告)日：2018-08-09

申请号：US15452746

申请日：2017-03-08

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Wei Feng ,  Ying-Chiao Wang ,  Tsung-Ying Tsai ,  Kai-Ping Chen ,  Chien-Ting Ho

IPC: H01L27/108 ,  H01L23/528

CPC classification number: H01L27/10885 ,  H01L23/5283 ,  H01L27/10897

Abstract: A semiconductor device includes a substrate, plural active areas, plural bit lines and plural dummy bit lines. The substrate includes a cell region and a periphery region, and the active areas are defined on the substrate. The bit lines are disposed on the substrate, within the cell region and across the active areas. The dummy bit lines are disposed at a side of the bit lines, wherein the dummy bit lines are in contact with each other and have different pitches therebetween.

公开(公告)号：US09773790B1

公开(公告)日：2017-09-26

申请号：US15456605

申请日：2017-03-13

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chien-Ting Ho ,  Li-Wei Feng ,  Ying-Chiao Wang ,  Yu-Chieh Lin

IPC: H01L27/108 ,  H01L29/423 ,  H01L29/45

CPC classification number: H01L27/10823 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10897

Abstract: A semiconductor device includes a substrate including at least a memory region defined therein and a plurality of memory cells formed in the memory region, a plurality of first connecting structures, a plurality of second connecting structures, a plurality of dummy nodes respectively disposed on the first connecting structures, and a plurality of first storage nodes respectively disposed on the second connecting structures. The first connecting structures respectively include a conductive portion and a first metal portion, and the second connecting structures respectively include the conductive portion and a second metal portion. The first metal portion and the second metal portion include the same material. And the first metal portion and the second metal portion include different heights.

公开(公告)号：US11508614B2

公开(公告)日：2022-11-22

申请号：US17082034

申请日：2020-10-28

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Wei Feng ,  Ying-Chiao Wang ,  Tzu-Tsen Liu ,  Tsung-Ying Tsai ,  Chien-Ting Ho

IPC: H01L21/764 ,  H01L21/108 ,  H01L21/02 ,  H01L27/24 ,  H01L27/108

Abstract: A semiconductor device and method of forming the same, the semiconductor device includes plural bit lines, plural conductive patterns, plural conductive pads and a spacer. The bit lines are disposed on a substrate, along a first direction. The conductive patterns are disposed on the substrate, along the first direction, wherein the conductive patterns and the bit lines are alternately arranged in a second direction perpendicular to the first direction. The conductive pads are arranged in an array and disposed over the conductive patterns and the bit lines. The spacer is disposed between the bit lines and the conductive patterns, under the conductive pads, wherein the spacers includes a tri-layered structure having a first layer, a second layer and a third layer, and the second layer includes a plurality of air gaps separated arranged along the first direction.

公开(公告)号：US10854676B2

公开(公告)日：2020-12-01

申请号：US15873909

申请日：2018-01-18

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Wei Feng ,  Ying-Chiao Wang ,  Tzu-Tsen Liu ,  Tsung-Ying Tsai ,  Chien-Ting Ho

IPC: H01L27/24 ,  H01L27/108 ,  H01L21/02 ,  H01L21/764

Abstract: A semiconductor device and method of forming the same, the semiconductor device includes plural bit lines, plural conductive patterns, plural conductive pads and a spacer. The bit lines are disposed on a substrate, along a first direction. The conductive patterns are disposed on the substrate, along the first direction, wherein the conductive patterns and the bit lines are alternately arranged in a second direction perpendicular to the first direction. The conductive pads are arranged in an array and disposed over the conductive patterns and the bit lines. The spacer is disposed between the bit lines and the conductive patterns, under the conductive pads, wherein the spacers includes a tri-layered structure having a first layer, a second layer and a third layer, and the second layer includes a plurality of air gaps separated arranged along the first direction.

公开(公告)号：US10763260B2

公开(公告)日：2020-09-01

申请号：US16216954

申请日：2018-12-11

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chien-Ting Ho ,  Shih-Fang Tzou ,  Chun-Yuan Wu ,  Li-Wei Feng ,  Yu-Chieh Lin ,  Ying-Chiao Wang ,  Tsung-Ying Tsai

IPC: H01L27/105 ,  H01L21/768 ,  H01L21/02 ,  H01L29/66 ,  H01L21/311 ,  H01L27/108 ,  H01L29/78 ,  H01L21/3105

Abstract: A semiconductor device includes a memory region, a plurality of bit lines in the memory region, a first low-k dielectric layer on each sidewall of each bit line, a plurality of storage node regions between the bit lines, and a second low-k dielectric layer surrounding each storage node region.

公开(公告)号：US20200035492A1

公开(公告)日：2020-01-30

申请号：US16592773

申请日：2019-10-04

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Wei Feng ,  Ming-Te Wei ,  Yu-Chieh Lin ,  Ying-Chiao Wang ,  Chien-Ting Ho

IPC: H01L21/033 ,  H01L21/02 ,  H01L27/108 ,  H01L21/3105 ,  H01L21/027

Abstract: A method for patterning a semiconductor structure is provided, including forming an additional third material layer on a thinner portion of a second material layer to be an etching buffer layer. The removed thickness of the thinner portion of the second material layer covered by the third material layer during an etching back process is therefore reduced.

公开(公告)号：US10546861B2

公开(公告)日：2020-01-28

申请号：US16516204

申请日：2019-07-18

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Tzu-Tsen Liu ,  Li-Wei Feng ,  Chien-Ting Ho

IPC: H01L27/108 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L29/08 ,  H01L29/41

Abstract: A semiconductor device and a manufacturing method thereof are provided. The method includes providing a substrate, a plurality of word lines and a plurality of bit lines, and then forming a storage node contact on each source/drain region, so that a width of a top surface of each storage node contact in a direction is less than a width of a bottom surface of each storage node contact.

公开(公告)号：US20190341385A1

公开(公告)日：2019-11-07

申请号：US16516204

申请日：2019-07-18

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Tzu-Tsen Liu ,  Li-Wei Feng ,  Chien-Ting Ho

IPC: H01L27/108 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L29/08

Abstract: A semiconductor device and a manufacturing method thereof are provided. The method includes providing a substrate, a plurality of word lines and a plurality of bit lines, and then forming a storage node contact on each source/drain region, so that a width of a top surface of each storage node contact in a direction is less than a width of a bottom surface of each storage node contact.

公开(公告)号：US10276650B2

公开(公告)日：2019-04-30

申请号：US15927103

申请日：2018-03-21

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Tzu-Chin Wu ,  Wei-Hsin Liu ,  Yi-Wei Chen ,  Chia-Lung Chang ,  Jui-Min Lee ,  Po-Chun Chen ,  Li-Wei Feng ,  Ying-Chiao Wang ,  Wen-Chieh Lu ,  Chien-Ting Ho ,  Tsung-Ying Tsai ,  Kai-Ping Chen

IPC: H01L27/108 ,  H01L49/02 ,  H01L29/94

Abstract: A semiconductor memory device includes a semiconductor substrate, a first support layer, a first electrode, a capacitor dielectric layer, and a second electrode. The first support layer is disposed on the semiconductor substrate. The first electrode is disposed on the semiconductor substrate and penetrates the first support layer. The capacitor dielectric layer is disposed on the first electrode. The second electrode is disposed on the semiconductor substrate, and at least a part of the capacitor dielectric layer is disposed between the first electrode and the second electrode. The first support layer includes a carbon doped nitride layer, and a carbon concentration of a bottom portion of the first support layer is higher than a carbon concentration of a top portion of the first support layer.