公开(公告)号：US20220165866A1

公开(公告)日：2022-05-26

申请号：US17143135

申请日：2021-01-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Chang ,  Yao-Hsien Chung ,  Shih-Wei Su ,  Hao-Hsuan Chang ,  Da-Jun Lin ,  Ting-An Chien ,  Bin-Siang Tsai

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/778

Abstract: An HEMT includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer is different from the composition of the second III-V compound layer. A trench is disposed within the first III-V compound layer and the second III-V compound layer. The trench has a first corner and a second corner. The first corner and the second corner are disposed in the first III-V compound layer. A first dielectric layer contacts a sidewall of the first corner. A second dielectric layer contacts a sidewall of the second corner. The first dielectric layer and the second dielectric layer are outside of the trench. A gate is disposed in the trench. A source electrode and a drain electrode are respectively disposed at two sides of the gate. A gate electrode is disposed directly on the gate.

公开(公告)号：US20220140239A1

公开(公告)日：2022-05-05

申请号：US17114438

申请日：2020-12-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Wei Su ,  Da-Jun Lin ,  Chih-Wei Chang ,  Bin-Siang Tsai ,  Ting-An Chien

IPC: H01L45/00 ,  H01L27/24

Abstract: The invention provides a semiconductor structure, the semiconductor structure includes a substrate, a resistance random access memory on the substrate, an upper electrode, a lower electrode and a resistance conversion layer between the upper electrode and the lower electrode, and a cap layer covering the outer side of the resistance random access memory, the cap layer has an upper half and a lower half, and the upper half and the lower half contain different stresses.

公开(公告)号：US11114612B2

公开(公告)日：2021-09-07

申请号：US16708389

申请日：2019-12-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Bin-Siang Tsai ,  Shih-Wei Su ,  Ting-An Chien

IPC: H01L43/02 ,  H01L43/12 ,  G11C11/16 ,  H01L27/22 ,  H01F10/32 ,  H01F41/34 ,  H01L43/10

Abstract: A method for fabricating semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, in which the MTJ stack includes a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer. Next, part of the MTJ stack is removed, a first cap layer is formed on a sidewall of the MTJ stack, and the first cap layer and the MTJ stack are removed to form a first MTJ and a second MTJ.

公开(公告)号：US20210143324A1

公开(公告)日：2021-05-13

申请号：US16708389

申请日：2019-12-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Bin-Siang Tsai ,  Shih-Wei Su ,  Ting-An Chien

IPC: H01L43/12 ,  H01L43/02 ,  G11C11/16 ,  H01F41/34 ,  H01L27/22 ,  H01F10/32

Abstract: A method for fabricating semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, in which the MTJ stack includes a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer. Next, part of the MTJ stack is removed, a first cap layer is formed on a sidewall of the MTJ stack, and the first cap layer and the MTJ stack are removed to form a first MTJ and a second MTJ.