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公开(公告)号：US12108681B2
公开(公告)日：2024-10-01
申请号：US18376820
申请日：2023-10-04
发明人： Da-Jun Lin , Tai-Cheng Hou , Bin-Siang Tsai , Ting-An Chien
摘要： A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a top electrode on the MTJ, a trapping layer in the top electrode for trapping hydrogen, a first inter-metal dielectric (IMD) layer on the MTJ, and a first metal interconnection in the first IMD layer and on the top electrode. Preferably, a top surface of the trapping layer is lower than a bottom surface of the first IMD layer.
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公开(公告)号：US12089512B2
公开(公告)日：2024-09-10
申请号：US18242550
申请日：2023-09-06
发明人： Shih-Wei Su , Da-Jun Lin , Chih-Wei Chang , Bin-Siang Tsai , Ting-An Chien
CPC分类号： H10N70/063 , H10B63/00 , H10N70/028 , H10N70/041 , H10N70/841 , H10N70/8833
摘要： The invention provides a semiconductor structure, the semiconductor structure includes a substrate, a resistance random access memory on the substrate, an upper electrode, a lower electrode and a resistance conversion layer between the upper electrode and the lower electrode, and a cap layer covering the outer side of the resistance random access memory, the cap layer has an upper half and a lower half, and the upper half and the lower half contain different stresses.
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公开(公告)号：US20240213304A1
公开(公告)日：2024-06-27
申请号：US18107521
申请日：2023-02-09
发明人： Da-Jun Lin , Bin-Siang Tsai , Fu-Yu Tsai , Chung-Yi Chiu
IPC分类号： H01L27/06 , H01L21/285 , H01L21/768 , H01L23/522 , H01L23/532
CPC分类号： H01L28/60 , H01L21/28556 , H01L21/76843 , H01L21/76877 , H01L23/5226 , H01L23/53228 , H01L23/53295 , H01L27/0629 , H01L27/0647
摘要： An MIM capacitor structure includes numerous inter-metal dielectrics. A trench is embedded within the inter-metal dielectrics. A capacitor is disposed within the trench. The capacitor includes a first electrode layer, a capacitor dielectric layer and a second electrode layer. The first electrode layer, the capacitor dielectric layer and the second electrode layer fill in and surround the trench. The capacitor dielectric layer is between the first electrode layer and the second electrode layer. A silicon oxide liner surrounds a sidewall of the trench and contacts the first electrode layer.
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公开(公告)号：US11871677B2
公开(公告)日：2024-01-09
申请号：US17180876
申请日：2021-02-22
发明人： Tai-Cheng Hou , Fu-Yu Tsai , Bin-Siang Tsai , Da-Jun Lin , Chau-Chung Hou , Wei-Xin Gao
摘要： A method for fabricating a semiconductor device includes the steps of: providing a substrate, wherein the substrate comprises a MRAM region and a logic region; forming a magnetic tunneling junction (MTJ) on the MRAM region; forming a top electrode on the MTJ; and then performing a flowable chemical vapor deposition (FCVD) process to form a first inter-metal dielectric (IMD) layer around the top electrode and the MTJ.
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公开(公告)号：US20230369436A1
公开(公告)日：2023-11-16
申请号：US17837054
申请日：2022-06-10
发明人： Da-Jun Lin , Fu-Yu Tsai , Bin-Siang Tsai , Chung-Yi Chiu
IPC分类号： H01L29/45 , H01L21/285 , H01L29/66 , H01L29/778 , H01L29/20
CPC分类号： H01L29/452 , H01L21/28575 , H01L29/66462 , H01L29/7787 , H01L29/2003
摘要： A method for forming ohmic contacts on a compound semiconductor device is disclosed. A channel layer is formed on a substrate. A barrier layer is formed on the channel layer. A passivation layer is formed on the barrier layer. A contact area is formed by etching through the passivation layer and the barrier layer. The channel layer is partially exposed at a bottom of the contact area. A sacrificial metallic layer is conformally deposited on the contact area. The sacrificial metallic layer is subjected to an annealing process, thereby forming a heavily doped region in the channel layer directly under the sacrificial metallic layer. The sacrificial metallic layer is removed to expose the heavily doped region. A metal silicide layer is formed on the heavily doped region.
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公开(公告)号：US20230369435A1
公开(公告)日：2023-11-16
申请号：US17835956
申请日：2022-06-08
发明人： Da-Jun Lin , Fu-Yu Tsai , Bin-Siang Tsai , Chung-Yi Chiu
IPC分类号： H01L29/45 , H01L29/20 , H01L29/205 , H01L29/778 , H01L29/40 , H01L21/285 , H01L29/66
CPC分类号： H01L29/452 , H01L29/2003 , H01L29/205 , H01L29/7786 , H01L29/401 , H01L21/28575 , H01L29/66462
摘要： A compound semiconductor device includes a substrate, a channel layer on the substrate, a barrier layer on the channel layer, a passivation layer on the barrier layer, and a contact area recessed into the passivation layer and the barrier layer. The channel layer is partially exposed at a bottom of the contact area. A bi-layer silicide film is disposed on the contact area. A copper contact is disposed on the bi-layer silicide film.
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公开(公告)号：US11818960B2
公开(公告)日：2023-11-14
申请号：US17394424
申请日：2021-08-05
发明人： Da-Jun Lin , Tai-Cheng Hou , Bin-Siang Tsai , Ting-An Chien
摘要： A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a top electrode on the MTJ, a trapping layer in the top electrode for trapping hydrogen, a first inter-metal dielectric (IMD) layer on the MTJ, and a first metal interconnection in the first IMD layer and on the top electrode. Preferably, a top surface of the trapping layer is lower than a bottom surface of the first IMD layer.
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公开(公告)号：US11793091B2
公开(公告)日：2023-10-17
申请号：US17114438
申请日：2020-12-07
发明人： Shih-Wei Su , Da-Jun Lin , Chih-Wei Chang , Bin-Siang Tsai , Ting-An Chien
CPC分类号： H10N70/063 , H10B63/00 , H10N70/028 , H10N70/041 , H10N70/841 , H10N70/8833
摘要： The invention provides a semiconductor structure, the semiconductor structure includes a substrate, a resistance random access memory on the substrate, an upper electrode, a lower electrode and a resistance conversion layer between the upper electrode and the lower electrode, and a cap layer covering the outer side of the resistance random access memory, the cap layer has an upper half and a lower half, and the upper half and the lower half contain different stresses.
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公开(公告)号：US20230329004A1
公开(公告)日：2023-10-12
申请号：US18209482
申请日：2023-06-14
发明人： Da-Jun Lin , Yi-An Shih , Bin-Siang Tsai , Fu-Yu Tsai
摘要： A method for fabricating a semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) on a substrate, forming a top electrode on the MTJ, forming an inter-metal dielectric (IMD) layer around the top electrode and the MTJ, forming a landing layer on the IMD layer and the MTJ, and then patterning the landing layer to form a landing pad. Preferably, the landing pad is disposed on the top electrode and the IMD layer adjacent to one side of the top electrode.
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公开(公告)号：US11723287B2
公开(公告)日：2023-08-08
申请号：US17956772
申请日：2022-09-29
发明人： Da-Jun Lin , Shih-Wei Su , Bin-Siang Tsai , Ting-An Chien
IPC分类号： H01L27/22 , H01L43/02 , H01L43/08 , H01L43/10 , H01L43/12 , H10N50/80 , H10B61/00 , H10N50/01 , H10N50/85
摘要： A magnetic tunnel junction (MTJ) device includes a bottom electrode, a reference layer, a tunnel barrier layer, a free layer and a top electrode. The bottom electrode and the top electrode are facing each other. The reference layer, the tunnel barrier layer and the free layer are stacked from the bottom electrode to the top electrode, wherein the free layer includes a first ferromagnetic layer, a spacer and a second ferromagnetic layer, wherein the spacer is sandwiched by the first ferromagnetic layer and the second ferromagnetic layer, wherein the spacer includes oxidized spacer sidewall parts, the first ferromagnetic layer includes first oxidized sidewall parts, and the second ferromagnetic layer includes second oxidized sidewall parts. The present invention also provides a method of manufacturing a magnetic tunnel junction (MTJ) device.
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