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公开(公告)号:US20230238455A1
公开(公告)日:2023-07-27
申请号:US18129095
申请日:2023-03-31
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Chih-Wei Chang , Yao-Hsien Chung , Shih-Wei Su , Hao-Hsuan Chang , Ting-An Chien , Bin-Siang Tsai
IPC: H01L29/778 , H01L29/66 , H01L29/20
CPC classification number: H01L29/7786 , H01L29/66462 , H01L29/2003
Abstract: A method for forming a high electron mobility transistor is disclosed. A substrate is provided. A channel layer is formed on the substrate. An electron supply layer is formed on the channel layer. A dielectric passivation layer is formed on the electron supply layer. A gate recess is formed into the dielectric passivation layer and the electron supply layer. A surface modification layer is conformally deposited on an interior surface of the gate recess. The surface modification layer is first subjected to the nitride treatment and is then subjected to the oxidation treatment. A P-type GaN layer is formed in the gate recess and on the surface modification layer.
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公开(公告)号:US11688802B2
公开(公告)日:2023-06-27
申请号:US17179322
申请日:2021-02-18
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Chih-Wei Chang , Yao-Hsien Chung , Shih-Wei Su , Hao-Hsuan Chang , Ting-An Chien , Bin-Siang Tsai
IPC: H01L29/778 , H01L29/66 , H01L29/20
CPC classification number: H01L29/7786 , H01L29/2003 , H01L29/66462
Abstract: A method for forming a high electron mobility transistor is disclosed. A substrate is provided. A channel layer is formed on the substrate. An electron supply layer is formed on the channel layer. A dielectric passivation layer is formed on the electron supply layer. A gate recess is formed into the dielectric passivation layer and the electron supply layer. A surface modification layer is conformally deposited on an interior surface of the gate recess. The surface modification layer is then subjected to an oxidation treatment or a nitridation treatment. A P-type GaN layer is formed in the gate recess and on the surface modification layer.
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公开(公告)号:US20190140074A1
公开(公告)日:2019-05-09
申请号:US15838243
申请日:2017-12-11
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Hao-Hsuan Chang , Yao-Hsien Chung , Fu-Yu Tsai
IPC: H01L29/66 , H01L21/8234 , H01L27/088
Abstract: A manufacturing method of a semiconductor device includes the following steps. A first stacked structure and a second stacked structure are formed on a core region and an input/output (I/O) region of a semiconductor substrate respectively. The first stacked structure includes a first patterned oxide layer, a first patterned nitride layer, and a first dummy gate. The second stacked structure includes a second patterned oxide layer, a second patterned nitride layer, and a second dummy gate. The first dummy gate and the second dummy gate are removed for forming a first recess above the core region and a second recess above the I/O region. A first gate structure is formed in the first recess and a second gate structure is formed in the second recess. The first patterned nitride layer is removed before the step of forming the first gate structure in the first recess.
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公开(公告)号:US10283618B1
公开(公告)日:2019-05-07
申请号:US15838243
申请日:2017-12-11
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Hao-Hsuan Chang , Yao-Hsien Chung , Fu-Yu Tsai
IPC: H01L21/338 , H01L21/8238 , H01L27/092 , H01L29/49 , H01L21/8234 , H01L29/165 , H01L29/66 , H01L27/088
Abstract: A manufacturing method of a semiconductor device includes the following steps. A first stacked structure and a second stacked structure are formed on a core region and an input/output (I/O) region of a semiconductor substrate respectively. The first stacked structure includes a first patterned oxide layer, a first patterned nitride layer, and a first dummy gate. The second stacked structure includes a second patterned oxide layer, a second patterned nitride layer, and a second dummy gate. The first dummy gate and the second dummy gate are removed for forming a first recess above the core region and a second recess above the I/O region. A first gate structure is formed in the first recess and a second gate structure is formed in the second recess. The first patterned nitride layer is removed before the step of forming the first gate structure in the first recess.
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公开(公告)号:US20230145175A1
公开(公告)日:2023-05-11
申请号:US18092916
申请日:2023-01-03
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Chih-Wei Chang , Yao-Hsien Chung , Shih-Wei Su , Hao-Hsuan Chang , Da-Jun Lin , Ting-An Chien , Bin-Siang Tsai
IPC: H01L29/66 , H01L29/778 , H01L29/20
CPC classification number: H01L29/66462 , H01L29/2003 , H01L29/7786
Abstract: A high electron mobility transistor includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer is different from that of the second III-V compound layer. A trench is disposed within the first III-V compound layer and the second III-V compound layer. The trench has a first corner and a second corner. The first corner and the second corner are disposed in the first III-V compound layer. A first dielectric layer contacts a sidewall of the first corner. A second dielectric layer contacts a sidewall of the second corner. The first dielectric layer and the second dielectric layer are outside of the trench. A gate is disposed in the trench. A source electrode and a drain electrode are respectively disposed at two sides of the gate. A gate electrode is disposed on the gate.
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公开(公告)号:US20220365433A1
公开(公告)日:2022-11-17
申请号:US17316736
申请日:2021-05-11
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Hao-Hsuan Chang , Da-Jun Lin , Yao-Hsien Chung , Ting-An Chien , Bin-Siang Tsai , Chih-Wei Chang , Shih-Wei Su , Hsu Ting , Sung-Yuan Tsai
Abstract: A fabricating method of reducing photoresist footing includes providing a silicon nitride layer. Later, a fluorination process is performed to graft fluoride ions onto a top surface of the silicon nitride layer. After the fluorination process, a photoresist is formed to contact the top surface of the silicon nitride layer. Finally, the photoresist is patterned to remove at least part of the photoresist contacting the silicon nitride layer.
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公开(公告)号:US20220262939A1
公开(公告)日:2022-08-18
申请号:US17179322
申请日:2021-02-18
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Chih-Wei Chang , Yao-Hsien Chung , Shih-Wei Su , Hao-Hsuan Chang , Ting-An Chien , Bin-Siang Tsai
IPC: H01L29/778 , H01L29/20 , H01L29/66
Abstract: A method for forming a high electron mobility transistor is disclosed. A substrate is provided. A channel layer is formed on the substrate. An electron supply layer is formed on the channel layer. A dielectric passivation layer is formed on the electron supply layer. A gate recess is formed into the dielectric passivation layer and the electron supply layer. A surface modification layer is conformally deposited on an interior surface of the gate recess. The surface modification layer is then subjected to an oxidation treatment or a nitridation treatment. A P-type GaN layer is formed in the gate recess and on the surface modification layer.
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公开(公告)号:US12015076B2
公开(公告)日:2024-06-18
申请号:US18092916
申请日:2023-01-03
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Chih-Wei Chang , Yao-Hsien Chung , Shih-Wei Su , Hao-Hsuan Chang , Da-Jun Lin , Ting-An Chien , Bin-Siang Tsai
IPC: H01L29/66 , H01L29/20 , H01L29/423 , H01L29/778
CPC classification number: H01L29/66462 , H01L29/2003 , H01L29/4236 , H01L29/42364 , H01L29/7786
Abstract: A high electron mobility transistor includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer is different from that of the second III-V compound layer. A trench is disposed within the first III-V compound layer and the second III-V compound layer. The trench has a first corner and a second corner. The first corner and the second corner are disposed in the first III-V compound layer. A first dielectric layer contacts a sidewall of the first corner. A second dielectric layer contacts a sidewall of the second corner. The first dielectric layer and the second dielectric layer are outside of the trench. A gate is disposed in the trench. A source electrode and a drain electrode are respectively disposed at two sides of the gate. A gate electrode is disposed on the gate.
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公开(公告)号:US11762293B2
公开(公告)日:2023-09-19
申请号:US17316736
申请日:2021-05-11
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Hao-Hsuan Chang , Da-Jun Lin , Yao-Hsien Chung , Ting-An Chien , Bin-Siang Tsai , Chih-Wei Chang , Shih-Wei Su , Hsu Ting , Sung-Yuan Tsai
CPC classification number: G03F7/0755 , G03F7/2043 , C23C16/345
Abstract: A fabricating method of reducing photoresist footing includes providing a silicon nitride layer. Later, a fluorination process is performed to graft fluoride ions onto a top surface of the silicon nitride layer. After the fluorination process, a photoresist is formed to contact the top surface of the silicon nitride layer. Finally, the photoresist is patterned to remove at least part of the photoresist contacting the silicon nitride layer.
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公开(公告)号:US20230163207A1
公开(公告)日:2023-05-25
申请号:US17834936
申请日:2022-06-08
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Chih-Wei Chang , Da-Jun Lin , Yao-Hsien Chung , Shih-Wei Su , Hao-Hsuan Chang , Ting-An Chien , Bin-Siang Tsai
IPC: H01L29/778 , H01L29/20 , H01L29/66
CPC classification number: H01L29/7786 , H01L29/2003 , H01L29/66462
Abstract: The invention provides a semiconductor structure, which comprises a GaN gallium nitride (GaN) layer, an aluminum gallium nitride (AlGaN) layer on the gallium nitride layer, a polarization boost layer on and in direct contact with the aluminum gallium nitride layer, and a gate liner layer on the polarization boost layer.
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