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公开(公告)号：US09779684B2
公开(公告)日：2017-10-03
申请号：US14906702
申请日：2015-12-22
发明人： Yafeng Li
IPC分类号： G09G3/36
CPC分类号： G09G3/3677 , G09G3/3648 , G09G3/3696 , G09G2230/00 , G09G2300/0408 , G09G2300/0809 , G09G2310/0286 , G11C19/28
摘要： A GOA circuit includes GOA circuit units coupled in series. Each GOA circuit unit includes an input control module, an output control module, a pull-down module, and a pull-up holding module. The input control module includes a first transistor, a second transistor, a third transistor, and a fourth transistor. Each GOA circuit unit includes ten transistors. Because the GOA circuit unit proposed by the present invention comprises fewer transistors, it is good for being used in displays with a narrow bezel. In addition, the GOA circuit unit comprises an input control module comprising a second transistor and a third transistor controlled by a first gate turn-on signal. A first transistor and the second transistor are connected in series, and the third transistor and a fourth transistor are connected in series, which reduces leakage current. It provides a beneficiary effect that the stability of the GOA circuit unit is improved.
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公开(公告)号：US20210124206A1
公开(公告)日：2021-04-29
申请号：US16308483
申请日：2018-09-27
发明人： Yafeng Li , Jinfang Wu
IPC分类号： G02F1/1362 , G02F1/1333 , G02F1/1343 , G06F3/041
摘要： The invention provides a TFT array substrate and LCD panel. the TFT array substrate comprises a first metal layer, a first interlayer insulating layer, a second metal layer, a second interlayer insulating layer and a third metal layer sequentially disposed above the substrate. The first, second and third metal layers comprise a plurality of first, second and third fanout lines in the fanout line area, respectively; two of the first, second, and third fanout lines are connected to the data lines, and the other is connected with the touch line; because the first interlayer insulating layer is disposed between the first and second fanout lines, and the second interlayer insulating layer is disposed between the third and second fanout lines, the first, second and third fanout lines can overlap, which can effectively reduce the fanout line area and help to achieve a narrow border.
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公开(公告)号：US10803809B2
公开(公告)日：2020-10-13
申请号：US15327304
申请日：2016-12-29
发明人： Yafeng Li
IPC分类号： G09G3/3266 , G09G3/36 , G09G3/20
摘要： Disclosed are a gate driving circuit, a driving method thereof, and a display device which comprises the gate driving circuit. In the gate driving circuit, the Qn node in the nth stage circuit is precharged when an output signal of a Qn−1 node in a previous stage driving circuit and an output signal of a Qn+1 node in a next stage driving circuit are both in a high-level state. Both the Qn−1 node and the Qn+1 node are at low levels when the gate driving circuit is in an All Gate On display state, and thus a possibility of current leakage from the Qn node can be substantially reduced.
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公开(公告)号：US10657918B2
公开(公告)日：2020-05-19
申请号：US15327303
申请日：2016-12-30
发明人： Yafeng Li
IPC分类号： G09G3/36
摘要： Disclosed is a gate driving circuit and a display device, which belongs to the technical field of displaying, and resolves a technical problem that a signal transmitted between cascaded gate driving circuits is easily attenuated in the prior art. The gate driving circuit includes a precharging unit circuit, an output unit circuit, and a compensation charging unit circuit; the output unit circuit includes a first reference point and a first clock signal line; and the precharging unit circuit is configured to input a high level to the first reference point before an output period.
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公开(公告)号：US10484655B2
公开(公告)日：2019-11-19
申请号：US15327301
申请日：2016-12-30
发明人： Yafeng Li
IPC分类号： H04N9/30 , G02F1/1345 , G09G3/36
摘要： Disclosed is a gate driving circuit and a display device, which solve the technical problem that the prior art is easy to cause abnormal output of gate driving signals. The gate driving circuit includes a precharge unit circuit, an output unit circuit, and a holding unit circuit. The output unit circuit includes a first reference point and a clock signal line. The holding unit circuit includes a second reference point and a holding signal line, and a holding capacitor is connected between the second reference point and the holding signal line.
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公开(公告)号：US10460652B2
公开(公告)日：2019-10-29
申请号：US15312197
申请日：2016-09-18
发明人： Yafeng Li
IPC分类号： G09G3/3208 , G09G3/36
摘要： The present application discloses a scanning driving circuit and a flat display apparatus, the scanning driving circuit includes a plurality of cascaded scanning driving unit, each scanning driving unit including a forward and reverse scanning circuit for controlling the forward or reverse scanning; an input circuit to perform charging to the pull-up control signal point and the pull-down control signal point; an output circuit for generating a scanning driving signal with two-valued high electrical level and outputting to the current level scanning line to drive a pixel unit.
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公开(公告)号：US10290262B2
公开(公告)日：2019-05-14
申请号：US15304497
申请日：2016-09-18
发明人： Yafeng Li
IPC分类号： G09G3/3266 , G09G3/36 , G09G3/20 , G11C19/28
摘要： The present disclosure provides a scanning drive circuit and a flat display device, the scanning drive circuit includes a plurality of cascaded scanning driving units, each scanning driving unit includes a forward-reverse scanning circuit used to control the forward scan and the reverse scan; a input circuit used to charge the pull-up and pull-down control signal point; a charge compensating circuit used to compensating charge the pull-up and pull-down control signal point; a output circuit generating the scanning driving signal to the present scanning line driving the pixel unit.
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公开(公告)号：US10255869B2
公开(公告)日：2019-04-09
申请号：US15506240
申请日：2016-12-30
发明人： Yafeng Li
摘要： The present invention relates to a GOA circuit. The GOA circuit comprises: a first thin film transistor (T1) to a fourteenth thin film transistor (T14), a first capacitor (C1) and a second capacitor (C2). The present invention adds a control unit consisted of thin film transistors (T9-T14) on the basis of the GOA circuit structure according to prior art, and a set of control signals (Select1, Select2) of which phases are opposite is introduced. The main function is to divide the gate output of the GOA circuit into two. In some special display mode, the frequency corresponded with Data signal will be halved, and the corresponding drive power consumption will be decreased. The present invention provides a GOA circuit, which can effectively reduce the layout space occupied by the GOA circuit for having a certain help to the development of the narrow frame technology.
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公开(公告)号：US10170067B2
公开(公告)日：2019-01-01
申请号：US15308843
申请日：2016-06-13
发明人： Yafeng Li
IPC分类号： G09G3/36 , G02F1/1345 , G02F1/1362 , G02F1/1368 , H01L27/12
摘要： A GOA electric circuit introduces a resistor and a timing signal, which are used to replace a second capacitor in the existing skills. One terminal of the resistor is connected to a constant high voltage level and the other terminal thereof is connected to a gate electrode of a ninth thin-film transistor. A source electrode of the ninth thin-film transistor is electrically connected to the timing signal. In the stage maintaining the output terminal at low voltage level, the voltage level of the second node can be changed between high and low voltage levels as the timing signal is changed, and the voltage level of the second node is pulled down in a specific frequency. This effectively prevents the second node from being at high voltage level for a long time and avoids the problem of threshold voltage shifting, and therefore improves the stability of GOA electric circuit.
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公开(公告)号：US10126343B2
公开(公告)日：2018-11-13
申请号：US14912924
申请日：2016-01-29
发明人： Yafeng Li , Xiangyi Peng
IPC分类号： G01R31/00 , G01R31/08 , G02F1/1362 , G02F1/1368 , G09G3/00 , G02F1/1333 , G09G3/36
摘要： The invention provides an ESD detection method for array substrate. By connecting the first metal layer on array substrate through the first wire to the first test point, connecting the second metal layer on array substrate through the second wire to the second test point, when ESD occurs on array substrate, the resistance detection device is used to measure the resistance between the first and second test points. If the resistance is positive infinity, ESD did not occur between the first and second metal layers; if the resistance is within a measurable range, ESD occurs between the first and second metal layers. The resistance is used to locate the location of ESD occurrence on array substrate. Compared to known method using microscope to search ESD location, the invention can locate ESD location on array substrate more accurately and rapidly to save time and labor as well as detection cost.
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