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公开(公告)号：US10796656B1
公开(公告)日：2020-10-06
申请号：US16308813
申请日：2018-09-27
发明人： Yafeng Li , Jinfang Wu
IPC分类号： G09G3/36
摘要： The invention provides a GOA circuit. The first node control module of the GOA circuit provided by the invention comprises a tenth TFT, an eleventh TFT and a twelfth TFT of N-type TFTs, when the voltage of the first node is high, the gate-to-source voltage difference of the twelfth TFT is the threshold voltage thereof, so that the drain-source voltage difference of the eleventh TFT is also the threshold voltage of the twelfth TFT, thereby making the resistance between the drain of the tenth TFT and the first node is extremely large, which can avoid the impact of leakage current generated by the tenth TFT on the voltage of the first node when the noise and coupling in the second node occurs, and to ensure the normal output of the scan signal.
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公开(公告)号：US10600380B2
公开(公告)日：2020-03-24
申请号：US15548414
申请日：2017-04-18
IPC分类号： G09G3/36 , H03K19/094 , G02F1/133 , G11C19/28
摘要： A scanning driving circuit includes a scanning-level-signal-generation module and a scanning-signal-output-module. The scanning-level-signal-generation module is configured to input an (N−1)th stage scanning signal, an (N+1)th stage scanning signal, and a reset signal, generate a scanning level signal based on the (N−1)th stage scanning signal, the (N+1)th stage scanning signal, and the reset signal, and hold the scanning level signal. The scanning-signal-output-module, connected to the scanning-level-signal-generation module, is configured to input a clock signal, and configured to output a scanning signal based in the scanning level signal and the clock signal.
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3.发明申请公开(公告)号：US20180314093A1
公开(公告)日：2018-11-01
申请号：US15529513
申请日：2017-03-15
发明人： Yafeng Li
IPC分类号： G02F1/1333 , G02F1/1368 , G02F1/1362 , G02F1/1339 , G02F1/1335 , G06F3/041
CPC分类号： G02F1/13338 , G02F1/133514 , G02F1/13394 , G02F2001/13396
摘要： The present invention provides an array substrate, a method of manufacturing the same and an In Cell touch control display panel. The array substrate of the present invention, by sequentially forming the first flat layer, the touch control signal layer, the second flat layer, the common electrode, the passivation layer, and pixel electrode on the source/drain electrode, the data line and the third insulating layer, such an architecture of which makes the touch control signal layer located under the second flat layer, would not be present in a manner that a region of a surface of the array substrate corresponding to the touch control signal layer forms protrusion, and a surface of said array substrate gets flatter so as to prevent the spacer from sliding to cause a manner of liquid crystal cell collapsing or alignment film scratching, promoting display quality; simultaneously, and makes three passivation layers of the conventional array substrate reduced into one passivation layer, and thereby simplifies manufacturing process, lower manufacturing process cost. In the manufacturing method of the array substrate of the present invention, the manufactured array substrate has a flatter surface, and a simplified manufacturing process, manufacturing process cost. The In Cell touch control display panel of the present invention has a great display quality, and a lower production cost, simultaneously.
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公开(公告)号：US10102820B2
公开(公告)日：2018-10-16
申请号：US15508106
申请日：2016-12-30
发明人： Yafeng Li
IPC分类号： G09G5/00 , G09G3/36 , G09G3/3266
摘要： The invention provides a GOA circuit, comprising a plurality of GOA units, for a positive integer n, n-th GOA unit comprising: a first TFT (T1), a second TFT (T2), a third TFT (T3), a fourth TFT T(4), a fifth TFT (T5), a sixth TFT (T6), a seventh TFT (T7), an eighth TFT (T8), a ninth TFT (T9), a first capacitor (C1) and a second capacitor (T2). The invention, based on known GOA circuit, uses T8 and T9 connected in parallel between node H and node Qn for conduction. The gate of T8 is connected to Qn−1 (the output signal of the previous GOA unit), and the gate of T9 is connected to Qn+1 (the output signal of the next GOA unit). The invention can provide the function of the known GOA circuit to prevent the stress on TFT T7, can also prevent the output Gn from instability.
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公开(公告)号：US20180174545A1
公开(公告)日：2018-06-21
申请号：US15128106
申请日：2016-08-31
发明人： Yafeng Li
IPC分类号： G09G3/36
CPC分类号： G09G3/3696 , G09G3/20 , G09G3/3648 , G09G3/3677 , G09G3/3688 , G09G2310/08 , G09G2330/021
摘要： The invention provides a GOA circuit, using the ninth and tenth TFTs and the resistor to control the voltage level of the third node, wherein ninth TFT having the gate connected to the m-th clock signal, the source connected to the first constant voltage, and the drain connected to one end of the resistor; the tenth TFT having the gate connected to the (m+2)-th clock signal, the source connected to the second constant voltage, and the drain connected to the other end of the resistor. Through the m-th and the (m+2)-th clock signal to control the ninth and the tenth TFTs to become conductive alternately, the present invention can charge and discharge the third node regularly to prevent the threshold voltage shift of the key TFT because the third node stays high for extended time, and ensure the stability of GOA circuit.
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公开(公告)号：US09935094B2
公开(公告)日：2018-04-03
申请号：US14912599
申请日：2016-01-29
发明人： Yafeng Li , Jinfang Wu
IPC分类号： G09G3/36 , G11C19/28 , H01L27/02 , H01L29/417 , G02F1/1362 , H01L27/12 , G02F1/1345
CPC分类号： H01L27/0207 , G02F1/13454 , G02F1/136213 , G09G3/3648 , G09G3/3674 , G09G3/3677 , G09G2310/0283 , G09G2310/0286 , H01L27/1214 , H01L29/41733
摘要： The present invention provides a GOA circuit based on LTPS semiconductor thin film transistor to control the voltage levels of the first node (Q(n)) and the second node (P(n)) with the forward scan direct current control signal (U2D) and the backward scan direct current control signal (D2U). The clock signal (CK(M)) is merely in charge of the output of the GOA unit of corresponding stage, which can effectively reduce the loading of the clock signal. It ensures that the entire loading of the clock signal after the GOA units of multiple stages are coupled to promote the output stability of the GOA circuit, and to realize the forward-backward scan of the GOA circuit. Moreover, the GOA unit of each stage comprises only ten thin film transistors, which is beneficial to reduce the layout space of the GOA circuit and to achieve the narrow frame design of the display device.
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公开(公告)号：US09875709B2
公开(公告)日：2018-01-23
申请号：US14917572
申请日：2016-01-28
发明人： Yafeng Li
IPC分类号： G09G3/34 , G09G3/36 , H01L27/12 , H01L29/786
CPC分类号： G09G3/3677 , G09G3/36 , G09G2300/0408 , G09G2310/0283 , G09G2310/0286 , G09G2310/0289 , G09G2310/0291 , G09G2310/08 , H01L27/1222 , H01L27/124 , H01L27/1255 , H01L29/78672
摘要： The invention provides a GOA circuit for LTPS-TFT, using a resistor (R1) and a tenth TFT (T10) to replace the second capacitor in known technology, and change the diode-style connection of the ninth TFT (T9) in known technology to connect one end of the resistor (R1) to the constant high voltage (VGH) and the other to the gate of the ninth TFT (T9) so that during the output end (G(n)) staying at low, the voltage of the second node (P(n)) follows the (M+1)-th clock signal (CK(M+1)) to switch between high and low, that is, following a fixed frequency to pull down the voltage of the second node (P(n)), prevents the second node from staying at high for long duration and prevents the sixth TFT (T6) and the seventh TFT (T7) from prolonged operation to cause threshold voltage shift and improve GOA circuit stability.
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公开(公告)号：US20170255308A1
公开(公告)日：2017-09-07
申请号：US14912601
申请日：2016-01-29
发明人： Yafeng Li , Xiangyi Peng
IPC分类号： G06F3/041 , G02F1/1335 , G02F1/1339 , G02F1/1362 , G02F1/1343 , G02F1/1333 , G02F1/1368
CPC分类号： G06F3/0412 , G02F1/133345 , G02F1/13338 , G02F1/133512 , G02F1/133514 , G02F1/13394 , G02F1/134309 , G02F1/134363 , G02F1/13439 , G02F1/136209 , G02F1/136286 , G02F1/1368 , G02F2001/133302 , G02F2001/133357 , G02F2001/13396 , G02F2001/13398 , G02F2201/121 , G02F2201/123 , G02F2201/40 , G02F2202/104 , G06F3/044
摘要： The present invention provides an in-cell touch display panel. In the in-cell touch display panel of the present invention, a first planarization layer (14) is solely arranged between a pixel electrode (15) and source/drain electrodes (45) located on one side of a TFT substrate (1) and the pixel electrode (15) is connected through a second via (141) formed in the first planarization layer (14) to the source/drain electrodes (45) so that compared to the prior art, the thickness of two passivation layers is omitted between the pixel electrode (15) and the source/drain electrodes (45) and negative influence caused by overlapping of vias between the first passivation layer (16) and the first planarization layer (14) and between the second passivation layer (18) and the first planarization layer (14) can be eliminated, whereby there is no need to take into consideration the relationship of the first planarization layer with respect to the first passivation layer and the second passivation layer in making a design so that the aperture ratio of the pixel can be greatly increased. Further, since the number of vias formed is reduced, the structure is simple and the manufacturing difficulty is lowered down to thereby improve product yield.
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公开(公告)号：US20240038780A1
公开(公告)日：2024-02-01
申请号：US17622791
申请日：2021-12-17
IPC分类号： H01L27/12
CPC分类号： H01L27/1248 , H01L27/1222
摘要： The present application sets forth an array substrate and a display terminal. The array substrate includes an underlay, a light shielding layer disposed on the underlay, an active layer disposed on the light shielding layer, and a connection element disposed on the active layer. The light shielding layer includes light shielding portions spaced from one another. The active layer includes active portions spaced from one another. The active portions correspond to the light shielding portions. Furthermore, adjacent two active portions are electrically connected through a bridge element. A toughness of the bridge element is greater than a toughness of the active portion.
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公开(公告)号：US10714509B2
公开(公告)日：2020-07-14
申请号：US15744615
申请日：2017-12-21
发明人： Yafeng Li , Jinfang Wu
摘要： The present disclosure provides a display panel including a display area and a non-display area, a base substrate, a plurality of thin film transistors, a plurality of touch signal lines, a first test signal line area, an array substrate row driving circuit, a second test signal line area, a ground line area and an insulating layer. The thin film transistor includes a gate, a gate insulating layer, a source and a drain. The non-display area includes a first side and a second side; the array substrate row driving circuit respectively forms a first gap and a second gap with the first test signal line area and the second test signal line area, an orthographic projection of the ground line area on the base substrate is in the projection of the second test signal line area in the base substrate. The present disclosure also provides a display device.
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