公开(公告)号：US20190114538A1

公开(公告)日：2019-04-18

申请号：US15786102

申请日：2017-10-17

Applicant: Xilinx, Inc.

Inventor： Aaron Ng ,  Elliott Delaye ,  Jindrich Zejda ,  Ashish Sirasao

IPC: G06N3/08 ,  G06F9/28 ,  H03K19/177 ,  G06F17/16

Abstract: In disclosed approaches of neural network processing, a host computer system copies an input data matrix from host memory to a shared memory for performing neural network operations of a first layer of a neural network by a neural network accelerator. The host instructs the neural network accelerator to perform neural network operations of each layer of the neural network beginning with the input data matrix. The neural network accelerator performs neural network operations of each layer in response to the instruction from the host. The host waits until the neural network accelerator signals completion of performing neural network operations of layer i before instructing the neural network accelerator to commence performing neural network operations of layer i+1, for i≥1. The host instructs the neural network accelerator to use a results data matrix in the shared memory from layer i as an input data matrix for layer i+1 for i≥1.

公开(公告)号：US20190114534A1

公开(公告)日：2019-04-18

申请号：US15785685

申请日：2017-10-17

Applicant: Xilinx, Inc.

Inventor： Xiao Teng ,  Aaron Ng ,  Ashish Sirasao ,  Elliott Delaye

IPC: G06N3/063 ,  G06N3/08 ,  G06N3/04

Abstract: At least one neural network accelerator performs operations of a first subset of layers of a neural network on an input data set, generates an intermediate data set, and stores the intermediate data set in a shared memory queue in a shared memory. A first processor element of a host computer system provides input data to the neural network accelerator and signals the neural network accelerator to perform the operations of the first subset of layers of the neural network on the input data set. A second processor element of the host computer system reads the intermediate data set from the shared memory queue, performs operations of a second subset of layers of the neural network on the intermediate data set, and generates an output data set while the neural network accelerator is performing the operations of the first subset of layers of the neural network on another input data set.

公开(公告)号：US10192016B2

公开(公告)日：2019-01-29

申请号：US15407875

申请日：2017-01-17

Applicant: Xilinx, Inc.

Inventor： Aaron Ng ,  Sabyasachi Das ,  Prabal Basu

IPC: G06F17/50

Abstract: Physical synthesis for a circuit design can include determining, using a processor, features relating to a signal path of the circuit design not meeting a timing requirement, processing the features through a first neural network model using the processor, wherein the first neural network model is trained to indicate an effectiveness of a first physical synthesis optimization, and selectively performing, using the processor, the first physical synthesis optimization for the signal path based upon a result from the first neural network model.

公开(公告)号：US09965581B1

公开(公告)日：2018-05-08

申请号：US14804134

申请日：2015-07-20

Applicant: Xilinx, Inc.

Inventor： Sabyasachi Das ,  Aaron Ng ,  Ruibing Lu ,  Niyati Shah ,  Zhiyong Wang

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/505 ,  G06F17/5077

Abstract: A method of circuit design may include synthesizing a circuit design using a processor and, for the synthesized circuit design, selectively reducing, using the processor, fanout of nets having a number of loads exceeding a first threshold number of loads and having a selected netlist connectivity. The method may include placing the circuit design using a processor and, for the placed circuit design, selectively reducing, using the processor, fanout of nets according to at least one of a number of loads or criticality.