公开(公告)号：US20110239168A1

公开(公告)日：2011-09-29

申请号：US13151208

申请日：2011-06-01

申请人： Junjiang Lei ,  Kuang-Hao Lay ,  Srini Doddi ,  Weiping Fang

发明人： Junjiang Lei ,  Kuang-Hao Lay ,  Srini Doddi ,  Weiping Fang

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G03F1/36

摘要： The present invention is directed to an improved method, system, and computer program product for accessing and analyzing patterns in the integrated circuit design. The method, system or computer program product includes generating an intelligent signature for a pattern. The derived pattern signature is an intelligent pattern identifier because it retains only essential information about a pattern that corresponds to lithography printable portions of the pattern. Accordingly, one pattern signature can represent a group of design patterns that are equivalents from a lithography perspective.

摘要翻译： 本发明涉及用于访问和分析集成电路设计中的图案的改进的方法，系统和计算机程序产品。 方法，系统或计算机程序产品包括为模式生成智能签名。 导出的图案签名是智能图案标识符，因为它仅保留关于对应于图案的可光刻印刷部分的图案的必要信息。 因此，一个图案签名可以表示与光刻方面相当的一组设计图案。

公开(公告)号：US20110167397A1

公开(公告)日：2011-07-07

申请号：US12955895

申请日：2010-11-29

申请人： Judy Huckabay ,  Weiping Fang ,  Chung-Shin Kang ,  Shiying Zhou

发明人： Judy Huckabay ,  Weiping Fang ,  Chung-Shin Kang ,  Shiying Zhou

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/5068

摘要： Some embodiments provide a method and system for identifying error markers for patterns within a design layout that do not meet the manufacturing constraints. Some embodiments extend a region from the error marked region to extract a pattern for decomposition analysis. Some embodiments compare the extracted pattern to known patterns stored in a library, which also stores at least one previously computed decomposition solution for each known pattern. For an extracted pattern existing within the library, some embodiments retrieve the previously computed decomposition solution from the library. For an extracted pattern that does not exist within the library, some embodiments use one or more simulations to determine a decomposition solution for the extracted pattern. The resulting decomposition solution replaces the extracted pattern within the design layout producing a variant of the original layout that contains the decomposed solution for the pattern.

摘要翻译： 一些实施例提供了用于识别不符合制造约束的设计布局内的图案的误差标记的方法和系统。 一些实施例将区域从错误标记区域扩展以提取用于分解分析的模式。 一些实施例将提取的图案与存储在库中的已知图案进行比较，库中还存储了每个已知图案的至少一个先前计算的分解解。 对于库中存在的提取模式，一些实施例从库中检索先前计算的分解解。 对于在库内不存在的提取模式，一些实施例使用一个或多个模拟来确定所提取模式的分解解。 所得到的分解解代替了设计布局中提取的图案，从而产生了原始布局的变体，该变体包含该模式的分解解。

公开(公告)号：US20090199137A1

公开(公告)日：2009-08-06

申请号：US12023512

申请日：2008-01-31

申请人： Judy Huckabay ,  Weiping Fang ,  Chung-Shin Kang ,  Shiying Zhou

发明人： Judy Huckabay ,  Weiping Fang ,  Chung-Shin Kang ,  Shiying Zhou

IPC分类号： G06F17/50 ,  G03F7/20

CPC分类号： G06F17/5068

摘要： Some embodiments provide a method and system for identifying error markers for patterns within a design layout that do not meet the manufacturing constraints. Some embodiments extend a region from the error marked region to extract a pattern for decomposition analysis. Some embodiments compare the extracted pattern to known patterns stored in a library, which also stores at least one previously computed decomposition solution for each known pattern. For an extracted pattern existing within the library, some embodiments retrieve the previously computed decomposition solution from the library. For an extracted pattern that does not exist within the library, some embodiments use one or more simulations to determine a decomposition solution for the extracted pattern. The resulting decomposition solution replaces the extracted pattern within the design layout producing a variant of the original layout that contains the decomposed solution for the pattern.

摘要翻译： 一些实施例提供了用于识别不符合制造约束的设计布局内的图案的误差标记的方法和系统。 一些实施例将区域从错误标记区域扩展以提取用于分解分析的模式。 一些实施例将提取的图案与存储在库中的已知图案进行比较，库中还存储了每个已知图案的至少一个先前计算的分解解。 对于库中存在的提取模式，一些实施例从库中检索先前计算的分解解。 对于在库内不存在的提取模式，一些实施例使用一个或多个模拟来确定所提取模式的分解解。 所得到的分解解代替了设计布局中提取的图案，从而产生了原始布局的变体，该变体包含该模式的分解解。

公开(公告)号：US07496884B2

公开(公告)日：2009-02-24

申请号：US11510415

申请日：2006-08-25

申请人： Weiping Fang ,  Huijuan Zhang ,  Yibing Wang ,  Zongwu Tang

发明人： Weiping Fang ,  Huijuan Zhang ,  Yibing Wang ,  Zongwu Tang

IPC分类号： G06F17/50

CPC分类号： G03F1/36 ,  G03F1/68

摘要： A system that verifies a simulated wafer image against an intended design. During operation, the system receives a design. Next, the system generates a skeleton from the design, wherein the skeleton specifies cell placements and associated bounding boxes for the cell placements, but does not include geometries for the cell placements. The system then computes environments for cell placements based on the skeleton. Next, the system generates templates for cell placements, wherein a template for a cell placement specifies the cell placement and the environment surrounding the cell placement. The system then generates the simulated wafer image by performing model-based simulations for cell placements associated with unique templates.

摘要翻译： 根据预期设计验证模拟晶片图像的系统。 在运行过程中，系统接收到一个设计。 接下来，系统从设计生成骨架，其中骨架指定单元格展示位置的单元格展示位置和相关联的边界框，但不包括单元格展示位置的几何。 然后系统基于骨架计算单元格展示位置的环境。 接下来，系统生成单元格展示位置的模板，其中单元格展示位置的模板指定单元格展示位置和单元格展示位置周围的环境。 然后，系统通过对与唯一模板相关联的单元格展示执行基于模型的模拟来生成模拟的晶片图像。