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    Semiconductor integrated circuit
    31.
    发明授权
    Semiconductor integrated circuit 有权
    半导体集成电路

    公开(公告)号：US08558602B2

    公开(公告)日：2013-10-15

    申请号：US12884533

    申请日：2010-09-17

    申请人： Ryo Fukuda ,  Masaru Koyanagi

    发明人： Ryo Fukuda ,  Masaru Koyanagi

    IPC分类号： H03L5/00

    CPC分类号： H03K3/356113

    摘要： According to one embodiment, a semiconductor integrated circuit includes first and second level shift circuits. The first level shifter includes a plurality of transistors and is connected to a power source voltage supply node of a first power source system and to which a first signal of a second power source system and a level inversion signal of the first signal are input. The second level shifter includes a plurality of transistors and is connected to the power source voltage supply node of the first power source system and to which the level inversion signal of the first signal of the second power source system and an output signal of the first level shifter are input. The first and second level shifters have substantially the same circuit configuration and driving abilities of corresponding ones of the transistors in the first and second level shifters are substantially set equal.

    摘要翻译： 根据一个实施例，半导体集成电路包括第一和第二电平移位电路。 第一电平移位器包括多个晶体管，并连接到第一电源系统的电源电压供应节点，第二电源系统的第一信号和第一信号的电平反转信号被输入到该第一电源系统。 第二电平移位器包括多个晶体管，并连接到第一电源系统的电源电压供应节点，并且第二电源系统的第一信号的电平反转信号和第一电平系统的输出信号 移位器被输入。 第一和第二电平移位器具有基本上相同的电路配置，并且第一和第二电平移位器中对应的晶体管的驱动能力基本上相等。

    Non-volatile semiconductor storage device
    32.
    发明授权
    Non-volatile semiconductor storage device 有权
    非易失性半导体存储器件

    公开(公告)号：US07911844B2

    公开(公告)日：2011-03-22

    申请号：US12337808

    申请日：2008-12-18

    申请人： Dai Nakamura ,  Hiroyuki Kutsukake ,  Kenji Gomikawa ,  Takeshi Shimane ,  Mitsuhiro Noguchi ,  Koji Hosono ,  Masaru Koyanagi ,  Takashi Aoi

    发明人： Dai Nakamura ,  Hiroyuki Kutsukake ,  Kenji Gomikawa ,  Takeshi Shimane ,  Mitsuhiro Noguchi ,  Koji Hosono ,  Masaru Koyanagi ,  Takashi Aoi

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0483 ,  G11C16/24

    摘要： A non-volatile semiconductor storage device includes: a memory cell array having memory cells arranged therein, the memory cells storing data in a non-volatile manner; and a plurality of transfer transistors transferring a voltage to the memory cells, the voltage to be supplied for data read, write and erase operations with respect to the memory cells. Each of the transfer transistors includes: a gate electrode formed on a semiconductor substrate via a gate insulation film; and diffusion layers formed to sandwich the gate electrode therebetween and functioning as drain/source layers. Upper layer wirings are provided above the diffusion layers and provided with a predetermined voltage to prevent depletion of the diffusion layers at least when the transfer transistors become conductive.

    摘要翻译： 非挥发性半导体存储装置包括：具有布置在其中的存储单元的存储单元阵列，所述存储单元以非易失性方式存储数据; 以及向存储单元传送电压的多个转移晶体管，用于相对于存储单元进行数据读取，写入和擦除操作的电压。 每个转移晶体管包括：通过栅极绝缘膜形成在半导体衬底上的栅电极; 以及形成为将栅极电极夹在其间并用作漏极/源极层的扩散层。 上层布线设置在扩散层上方，并具有预定电压，以至少在传输晶体管导通时防止扩散层的耗尽。

    Semiconductor device having auto trimming function for automatically adjusting voltage
    34.
    发明授权
    Semiconductor device having auto trimming function for automatically adjusting voltage 失效
    具有自动修整功能的半导体器件，用于自动调节电压

    公开(公告)号：US07359255B2

    公开(公告)日：2008-04-15

    申请号：US11438345

    申请日：2006-05-23

    申请人： Tohru Kimura ,  Masahiro Yoshihara ,  Masaru Koyanagi

    发明人： Tohru Kimura ,  Masahiro Yoshihara ,  Masaru Koyanagi

    IPC分类号： G11C7/00

    CPC分类号： H03M1/1061 ,  G11C5/147 ,  G11C16/30 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028

    摘要： A reference voltage generation circuit generates a reference voltage. An internal voltage generation circuit generates an internal voltage on the basis of the reference voltage generated by the reference voltage generation circuit. A first trimming circuit trims the internal voltage. During trimming of the internal voltage, the first trimming circuit trims an externally supplied first target voltage in accordance with first trimming data. The first trimming circuit ends the trimming when the first target voltage meets a given condition for the reference voltage.

    摘要翻译： 参考电压产生电路产生参考电压。 内部电压产生电路基于由参考电压产生电路产生的参考电压产生内部电压。 第一个微调电路修剪内部电压。 在微调内部电压期间，第一微调电路根据第一微调数据修正外部提供的第一目标电压。 当第一目标电压满足参考电压的给定条件时，第一微调电路结束修整。

    Semiconductor memory
    36.
    发明申请
    Semiconductor memory 失效
    半导体存储器

    公开(公告)号：US20050152205A1

    公开(公告)日：2005-07-14

    申请号：US11013688

    申请日：2004-12-17

    申请人： Katsuki Matsudera ,  Kazuhide Yoneya ,  Masaru Koyanagi

    发明人： Katsuki Matsudera ,  Kazuhide Yoneya ,  Masaru Koyanagi

    IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C11/407 ,  G11C8/00

    CPC分类号： G11C7/1066 ,  G11C7/1006 ,  G11C7/1051 ,  G11C2207/107

    摘要： A semiconductor memory includes a converter configured to convert each read-data of plural bits read from a memory core into serial data, respectively, in synchronization with a read clock to generate converted read-data. An output register holds the converted read-data in synchronization with the read clock. A selector selects one bit from each plural bits of the converted read-data, in accordance with a control data, and to supply the selected bit to the output register.

    摘要翻译： 半导体存储器包括：转换器，被配置为与读取时钟同步地分别将从存储器芯读取的多个位的每个读取数据转换为串行数据，以产生转换的读取数据。 输出寄存器与读取时钟同步地保存转换的读取数据。 选择器根据控制数据从转换的读取数据的每个多个比特中选择一个比特，并将所选择的比特提供给输出寄存器。

    MOS-type semiconductor integrated circuit
    37.
    发明授权
    MOS-type semiconductor integrated circuit 失效
    MOS型半导体集成电路

    公开(公告)号：US06714615B2

    公开(公告)日：2004-03-30

    申请号：US10234115

    申请日：2002-09-05

    申请人： Katsuki Matsudera ,  Masaru Koyanagi

    发明人： Katsuki Matsudera ,  Masaru Koyanagi

    IPC分类号： H03K19094

    CPC分类号： H03K19/0963 ,  H03K19/00315

    摘要： An MOS-type semiconductor integrated circuit has two MOS transistors of the opposite conductivity channel types connected in series between a high-voltage potential terminal and a ground potential terminal. Those two MOS transistors constitute an inverter and their gates are connected together to an input node. As output nodes, first and second nodes are provided with a current path in between which includes transistors whose gates are connected to the high-voltage potential terminal. A current path including the first transistor which constitutes a switch is inserted between the first node and the output node, and a current path including the second transistor and a barrier transistor is inserted between the second node and the output node. The gates of the first and second transistors are respectively connected with complementary clock signals. The bate of the barrier transistor is connected to the high-voltage potential terminal.

    摘要翻译： MOS型半导体集成电路具有串联连接在高压电位端子和接地电位端子之间的相反导电沟道型的两个MOS晶体管。 这两个MOS晶体管构成一个反相器，它们的栅极连接在一起到一个输入节点。 作为输出节点，第一和第二节点之间设置有电流路径，其间包括其栅极连接到高压电位端子的晶体管。 包括构成开关的第一晶体管的电流路径被插入在第一节点和输出节点之间，并且包括第二晶体管和势垒晶体管的电流路径被插入在第二节点和输出节点之间。 第一和第二晶体管的栅极分别与互补时钟信号连接。 势垒晶体管的端子连接到高压电位端子。

    MOS-type semiconductor integrated circuit
    38.
    发明授权
    MOS-type semiconductor integrated circuit 有权

    公开(公告)号：US06480034B1

    公开(公告)日：2002-11-12

    申请号：US09520632

    申请日：2000-03-07

    申请人： Katsuki Matsudera ,  Masaru Koyanagi

    发明人： Katsuki Matsudera ,  Masaru Koyanagi

    IPC分类号： H03K19094

    CPC分类号： H03K19/0963 ,  H03K19/00315

    摘要： An MOS-type semiconductor integrated circuit has two MOS transistors of the opposite conductivity channel types connected in series between a high-voltage potential terminal and a ground potential terminal. Those two MOS transistors constitute an inverter and their gates are connected together to an input node. As output nodes, first and second nodes are provided with a current path in between which includes transistors whose gates are connected to the high-voltage potential terminal. A current path including the first transistor which constitutes a switch is inserted between the first node and the output node, and a current path including the second transistor and a barrier transistor is inserted between the second node and the output node. The gates of the first and second transistors are respectively connected with complementary clock signals. The bate of the barrier transistor is connected to the high-voltage potential terminal.

    Semiconductor integrated circuit having first and second voltage step down circuits
    39.
    发明授权
    Semiconductor integrated circuit having first and second voltage step down circuits 失效
    具有第一和第二降压电路的半导体集成电路

    公开(公告)号：US5990729A

    公开(公告)日：1999-11-23

    申请号：US959774

    申请日：1997-10-29

    申请人： Eiji Kozuka ,  Masaru Koyanagi

    发明人： Eiji Kozuka ,  Masaru Koyanagi

    IPC分类号： G11C11/413 ,  G05F1/46 ,  G11C11/407 ,  G05F3/02

    CPC分类号： G05F1/465

    摘要： A semiconductor integrated circuit can precisely identify the level of an external input signal by stably supplying an internally stepped down voltage. It comprises a first N-channel MOS transistor having its drain/source connected between an external voltage supply node supplied with an external voltage and a first step-down output node for outputting a first stepped down voltage and its gate supplied with a control voltage higher than the external voltage, a first circuit supplied with the first stepped down voltage as operating voltage from the first step-down output node, a second N-channel MOS transistor having its drain/source connected between the external voltage supply node and a second step-down output node for outputting a second stepped down voltage and its gate supplied with the control voltage higher than the external voltage and having a drive capacity different from that of the first N-channel MOS transistor, the second step-down output node being separated from the first step-down output node and a second circuit supplied with the second stepped down voltage as operating voltage from the second step-down output node.

    摘要翻译： 半导体集成电路可以通过稳定地提供内部降压来精确地识别外部输入信号的电平。 它包括第一N沟道MOS晶体管，其漏极/源极连接在提供有外部电压的外部电压供应节点和用于输出第一降压电压的第一降压输出节点之间，并且其栅极被提供有较高的控制电压 提供第一降压电压的第一电路作为来自第一降压输出节点的工作电压的第二N沟道MOS晶体管，其漏极/源极连接在外部电压供应节点和第二步骤之间 输出节点，用于输出第二降压电压，其栅极被提供有比外部电压高的控制电压，并具有与第一N沟道MOS晶体管不同的驱动电容，第二降压输出节点被分离 从第一降压输出节点和第二降压电压提供的第二电路作为来自第二降压输出节点的工作电压。

    Semiconductor integrated circuit applicable to data read circuit from memory
    40.
    发明授权
    Semiconductor integrated circuit applicable to data read circuit from memory 失效
    半导体集成电路适用于存储器中的数据读取电路

    公开(公告)号：US5659512A

    公开(公告)日：1997-08-19

    申请号：US615364

    申请日：1996-03-13

    申请人： Masaru Koyanagi ,  Tsuyoshi Etoh

    发明人： Masaru Koyanagi ,  Tsuyoshi Etoh

    IPC分类号： G11C7/10 ,  G11C11/409 ,  G11C11/4096 ,  H01L27/10 ,  G11C7/00

    CPC分类号： G11C7/1048 ,  G11C11/4096 ,  G11C7/1051 ,  G11C7/1069

    摘要： A semiconductor integrated circuit includes a cell matrix having a large number of DRAM cells in a matrix shape; a plurality of bit line pairs which have a plurality of bit lines; a plurality of bit line differential amplifier circuits each provided in each pair of bit lines for amplifying a potential difference between the first and second bit lines; a pair of data lines for receiving a charge transmission from the bit line pairs and having a first data line connected to the first bit lines and a second data line connected to the second bit lines; a switch circuit for turning on/off the charge transmission from each bit line pair to the data line pair; a data line differential amplifier circuit for amplifying the potential difference between the first and second bit lines of the data line pair; and an amplitude limiting circuit including a transistor which has a source electrode connected to anyone of the first and second data lines, a drain electrode connected to the other of the first and second data lines, and a gate electrode having a gate potential set in the manner that the gate is conductive when the potential difference between the first and second data lines becomes a predetermined regulated value while the data line differential amplifier circuit is activated, thereby limiting an amplitude between the first and second data lines less than the predetermined regulated value by means of a conduction of the transistor.

    摘要翻译： 半导体集成电路包括具有矩阵形状的大量DRAM单元的单元矩阵; 具有多个位线的多个位线对; 多个位线差分放大器电路，分别设置在每对位线中，用于放大第一和第二位线之间的电位差; 一对数据线，用于从所述位线对接收电荷传输，并具有连接到所述第一位线的第一数据线和连接到所述第二位线的第二数据线; 用于将每个位线对的电荷传输开/关的数据线对的开关电路; 数据线差分放大器电路，用于放大数据线对的第一和第二位线之间的电位差; 以及包括晶体管的限幅电路，所述晶体管具有与所述第一和第二数据线中的任何一个连接的源电极，连接到所述第一和第二数据线中的另一个的漏电极，以及栅电极， 当数据线差分放大器电路被激活时，当第一和第二数据线之间的电位差成为预定的调节值时栅极导通，从而将第一和第二数据线之间的幅度限制在小于预定的调节值之前， 晶体管导通的手段。