公开(公告)号：US08619680B2

公开(公告)日：2013-12-31

申请号：US13366032

申请日：2012-02-03

申请人： Motoki Morita ,  Yasuhiko Matsunaga

发明人： Motoki Morita ,  Yasuhiko Matsunaga

IPC分类号： H04Q7/00 ,  H04J3/16

CPC分类号： H04W72/082 ,  H04W16/10 ,  H04W52/244 ,  H04W84/045 ,  H04W88/08

摘要： A base station includes a radio communication unit, a resource adjustment unit, a resource division unit and a detection unit. The resource adjustment unit determines radio resources to be allocated to a downlink communication from a radio resource region shared with another base station. The resource division unit limits, to a first radio resource segment which is a part of the radio resource region, radio resources in response to estimating that communication quality of the downlink communication using the limited first radio resource segment is improved over the communication quality of the first downlink communication when using the entire range of the radio resource region that is shared with the other base station. The detection unit detects execution of resource division by the other base station for limiting radio resources used for another downlink communication between the other base station and a mobile station to a second radio resource segment.

摘要翻译： 基站包括无线电通信单元，资源调整单元，资源划分单元和检测单元。 资源调整单元从与另一基站共享的无线资源区域确定要分配给下行链路通信的无线资源。 所述资源分割单元对作为所述无线资源区域的一部分的第一无线资源段限制无线资源，所述无线资源响应于使用所述受限的第一无线资源段的所述下行通信的通信质量相对于 当使用与另一个基站共享的无线电资源区域的整个范围时的第一下行链路通信。 检测单元检测另一基站的资源划分的执行，用于将用于另一基站与移动台之间的另一下行链路通信的无线资源限制到第二无线电资源段。

公开(公告)号：US20130157680A1

公开(公告)日：2013-06-20

申请号：US13818155

申请日：2011-08-17

申请人： Motoki Morita ,  Kojiro Hamabe ,  Yasuhiko Matsunaga

发明人： Motoki Morita ,  Kojiro Hamabe ,  Yasuhiko Matsunaga

IPC分类号： H04W72/08

CPC分类号： H04W72/082 ,  H04B17/26 ,  H04W24/08 ,  H04W52/225 ,  H04W52/244 ,  H04W84/105

摘要： In order to effectively determine an optimized radio resource, a radio communication system (100) includes a plurality of first base stations (111) and a plurality of first mobile stations (112) respectively connected to the plurality of first base stations (111). In the radio communication system (100), there are included calculation means (103) for calculating a statistic (130) by aggregating interference levels of radio waves between the plurality of first base stations (111) and second mobile stations (122) connected to a second base station (121) that forms a second cell (120) larger than a first cell (110) formed by each of the first base stations (111); and determination means (104) for determining, based on the statistic (130), a radio resource to be used by the plurality of first base stations (111) or the plurality of first mobile stations (112).

摘要翻译： 为了有效地确定优化的无线电资源，无线电通信系统（100）包括分别连接到多个第一基站（111）的多个第一基站（111）和多个第一移动台（112）。 在无线电通信系统（100）中，包括计算装置（103），用于通过聚合多个第一基站（111）和第二移动站（122）之间的无线电波的干扰电平来计算统计量（130） 第二基站（121），形成比由所述第一基站（111）中的每一个形成的第一小区（110）大的第二小区（120）。 以及用于根据所述统计（130）确定要由所述多个第一基站（111）或所述多个第一移动站（112）使用的无线电资源的确定装置（104）。

公开(公告)号：US20120037976A1

公开(公告)日：2012-02-16

申请号：US13235948

申请日：2011-09-19

申请人： Kikuko Sugimae ,  Masayuki Ichige ,  Fumitaka Arai ,  Yasuhiko Matsunaga ,  Atsuhiro Sato

发明人： Kikuko Sugimae ,  Masayuki Ichige ,  Fumitaka Arai ,  Yasuhiko Matsunaga ,  Atsuhiro Sato

IPC分类号： H01L27/105

CPC分类号： H01L27/115 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/30 ,  H01L27/11521 ,  H01L27/11524

摘要： A nonvolatile semiconductor memory includes a memory cell transistor including a first floating gate electrode layer formed on a first tunneling insulating film, a first inter-gate insulating film, first and second control gate electrode layers, and a first metallic silicide film; a high voltage transistor including a high voltage gate electrode layer formed on a high voltage gate insulating film, a second inter-gate insulating film having an aperture, third and fourth control gate electrode layers, and a second metallic silicide film; a low voltage transistor including a second floating gate electrode layer formed on a second tunneling insulating film, a third inter-gate insulating film having an aperture, fifth and sixth control gate electrode layers, and a third metallic silicide film; and a liner insulating film directly disposed on source and drain regions of each of the memory cell transistor, the low voltage transistor, and the high voltage transistor.

摘要翻译： 非易失性半导体存储器包括：存储单元晶体管，包括形成在第一隧穿绝缘膜上的第一浮栅电极层，第一栅间绝缘膜，第一和第二控制栅极电极层以及第一金属硅化物膜; 包括形成在高压栅极绝缘膜上的高电压栅极电极层，具有孔径的第二栅极间绝缘膜，第三和第四控制栅极电极层以及第二金属硅化物膜的高压晶体管; 包括形成在第二隧道绝缘膜上的第二浮栅电极层，具有孔的第三栅间绝缘膜，第五和第六控制栅电极层和第三金属硅化物膜的低压晶体管; 以及直接设置在每个存储单元晶体管，低压晶体管和高压晶体管的源极和漏极区域上的衬垫绝缘膜。

公开(公告)号：US08098527B2

公开(公告)日：2012-01-17

申请号：US12649822

申请日：2009-12-30

申请人： Koichi Fukuda ,  Dai Nakamura ,  Yasuhiko Matsunaga

发明人： Koichi Fukuda ,  Dai Nakamura ,  Yasuhiko Matsunaga

IPC分类号： G11C11/34

CPC分类号： H01L27/11519 ,  G11C16/0483 ,  H01L27/0207 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11529

摘要： A semiconductor memory device includes a semiconductor substrate; a memory cell array on the semiconductor substrate, the memory cell array comprising a plurality of memory cells capable of electrically storing data; a sense amplifier configured to detect the data stored in at least one of the memory cells; a cell source driver electrically connected to source side terminals of the memory cells and configured to supply a source potential to at least one of the source side terminals of the memory cells; a first wiring configured to electrically connect between at least one of the source side terminals of the memory cells and the cell source driver; and a second wiring formed in a same wiring layer as the first wiring, the second wiring being insulated from the first wiring and being electrically connected to the sense amplifier, wherein the first wiring and the second wiring have a plurality of through holes provided at a predetermined interval.

摘要翻译： 半导体存储器件包括半导体衬底; 所述存储单元阵列包括能够电存储数据的多个存储单元;存储单元阵列， 感测放大器，被配置为检测存储在所述存储器单元中的至少一个中的数据; 电池源驱动器，电连接到存储器单元的源极端子，并且被配置为向存储器单元的至少一个源极侧端子提供源极电位; 第一布线，被配置为电连接所述存储单元的至少一个源极端子和所述单元源驱动器; 以及形成在与所述第一布线相同的布线层中的第二布线，所述第二布线与所述第一布线绝缘并且电连接到所述读出放大器，其中所述第一布线和所述第二布线具有设置在所述第一布线的多个通孔 预定间隔。

公开(公告)号：US20110263244A1

公开(公告)日：2011-10-27

申请号：US13063857

申请日：2009-08-25

申请人： Kosei Kobayashi ,  Yasuhiko Matsunaga

发明人： Kosei Kobayashi ,  Yasuhiko Matsunaga

IPC分类号： H04W24/00

CPC分类号： H04W24/08 ,  H04W24/10

摘要： A mobile terminal includes a measuring unit that measures at least the moving speed of the self terminal and communication quality of wireless communication, and a communication unit that transmits terminal information including moving speed information and communication quality information. A quality monitoring apparatus (90) includes a terminal information collection unit (901) that collects the terminal information from at least one mobile terminal, and a terminal information classification unit (903) and a quality analyzing unit (904) that monitor communication quality in a predetermined target area for each moving speed range of the mobile terminal based on the collected terminal information.

摘要翻译： 移动终端包括至少测量自身终端的移动速度和无线通信的通信质量的测量单元，以及发送包括移动速度信息和通信质量信息的终端信息的通信单元。 质量监视装置（90）包括从至少一个移动终端收集终端信息的终端信息收集单元（901），以及监视通信质量的终端信息分类单元（903）和质量分析单元（904） 基于所收集的终端信息对移动终端的每个移动速度范围的预定目标区域。

公开(公告)号：US20100173471A1

公开(公告)日：2010-07-08

申请号：US12720062

申请日：2010-03-09

申请人： Kikuko Sugimae ,  Masayuki Ichige ,  Fumitaka Arai ,  Yasuhiko Matsunaga ,  Atsuhiro Sato

发明人： Kikuko Sugimae ,  Masayuki Ichige ,  Fumitaka Arai ,  Yasuhiko Matsunaga ,  Atsuhiro Sato

IPC分类号： H01L21/336 ,  H01L21/762

CPC分类号： H01L27/115 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/30 ,  H01L27/11521 ,  H01L27/11524

摘要： A nonvolatile semiconductor memory includes a memory cell transistor including a first floating gate electrode layer formed on a first tunneling insulating film, a first inter-gate insulating film, a first and a second control gate electrode layer, and a first metallic silicide film; a high voltage transistor including a high voltage gate electrode layer formed on the high voltage gate insulating film, a second inter-gate insulating film having an aperture, a third and a fourth control gate electrode layer, and a second metallic silicide film; a low voltage transistor including a second floating gate electrode layer formed on the second tunneling insulating film, a third inter-gate insulating film having an aperture, a fifth and a sixth control gate electrode layer, and a third metallic silicide film; and a liner insulating film directly disposed on a first source and drain region of the memory cell transistor, a second source and drain region of the low voltage transistor, and a third source and drain region of the high voltage transistor.

摘要翻译： 非易失性半导体存储器包括：存储单元晶体管，包括形成在第一隧道绝缘膜上的第一浮栅电极层，第一栅间绝缘膜，第一和第二控制栅极电极层和第一金属硅化物膜; 包括形成在高压栅极绝缘膜上的高电压栅极电极层，具有孔径的第二栅极间绝缘膜，第三和第四控制栅极电极层和第二金属硅化物膜的高压晶体管; 包括形成在第二隧道绝缘膜上的第二浮栅电极层，具有孔的第三栅间绝缘膜，第五和第六控制栅极电极层和第三金属硅化物膜的低压晶体管; 以及直接设置在存储单元晶体管的第一源极和漏极区域，低压晶体管的第二源极和漏极区域以及高压晶体管的第三源极和漏极区域中的衬垫绝缘膜。

公开(公告)号：US07705394B2

公开(公告)日：2010-04-27

申请号：US11553661

申请日：2006-10-27

申请人： Kikuko Sugimae ,  Masayuki Ichige ,  Fumitaka Arai ,  Yasuhiko Matsunaga ,  Atsuhiro Sato

发明人： Kikuko Sugimae ,  Masayuki Ichige ,  Fumitaka Arai ,  Yasuhiko Matsunaga ,  Atsuhiro Sato

IPC分类号： H01L27/115

CPC分类号： H01L27/115 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/30 ,  H01L27/11521 ,  H01L27/11524

摘要： A nonvolatile semiconductor memory includes a memory cell transistor including a first floating gate electrode layer formed on a first tunneling insulating film, a first inter-gate insulating film, first and second control gate electrode layers, and a first metallic silicide film; a high voltage transistor including a high voltage gate electrode layer formed on the high voltage gate insulating film, a second inter-gate insulating film having an aperture, third and fourth control gate electrode layers, and a second metallic silicide film; a low voltage transistor including a second floating gate electrode layer formed on a second tunneling insulating film, a third inter-gate insulating film having an aperture, fifth and sixth control gate electrode layers, and a third metallic silicide film; and a liner insulating film directly disposed on first, second and third source and drain regions of the memory cell transistor, low voltage transistor, and high voltage transistor, respectively.

摘要翻译： 非易失性半导体存储器包括：存储单元晶体管，包括形成在第一隧穿绝缘膜上的第一浮栅电极层，第一栅间绝缘膜，第一和第二控制栅极电极层以及第一金属硅化物膜; 包括形成在高电压栅极绝缘膜上的高电压栅极电极层，具有孔径的第二栅极间绝缘膜，第三和第四控制栅极电极层以及第二金属硅化物膜的高压晶体管; 包括形成在第二隧道绝缘膜上的第二浮栅电极层，具有孔的第三栅间绝缘膜，第五和第六控制栅电极层和第三金属硅化物膜的低压晶体管; 以及分别直接设置在存储单元晶体管，低压晶体管和高压晶体管的第一，第二和第三源极和漏极区上的衬垫绝缘膜。

公开(公告)号：US07615485B2

公开(公告)日：2009-11-10

申请号：US11877833

申请日：2007-10-24

申请人： Hiroyuki Kutsukake ,  Yasuhiko Matsunaga ,  Shoichi Miyazaki

发明人： Hiroyuki Kutsukake ,  Yasuhiko Matsunaga ,  Shoichi Miyazaki

IPC分类号： H01L23/535

CPC分类号： H01L23/485 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11529 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor device including forming two first gate electrodes along a first direction on a first surface of a semiconductor substrate and source/drain areas sandwiching a channel region under each of the first gate electrodes, forming a first interlayer insulating layer to fill a region between the first gate electrodes, lowering a top of the first interlayer insulating layer, depositing a second interlayer insulating layer on the first interlayer insulating layer and the first gate electrodes, planarizing a surface of the second interlayer insulating layer, and forming an interconnect layer in the second interlayer insulating layer and a contact plug in the first interlayer insulating layer and the second interlayer insulating layer so that the contact plug is in contact with the interconnect layer and one of the source/drain areas.

摘要翻译： 一种制造半导体器件的方法，包括在半导体衬底的第一表面上沿着第一方向形成两个第一栅电极和在每个第一栅电极下夹着沟道区的源/漏区，形成第一层间绝缘层以填充 在所述第一栅电极之间的区域中，降低所述第一层间绝缘层的顶部，在所述第一层间绝缘层上沉积第二层间绝缘层和所述第一栅电极，使所述第二层间绝缘层的表面平坦化，以及形成互连 层和第一层间绝缘层和第二层间绝缘层中的接触塞，使得接触插塞与互连层和源极/漏极区之一接触。

公开(公告)号：US20090270106A1

公开(公告)日：2009-10-29

申请号：US12302147

申请日：2007-05-29

申请人： Yasuhiko Matsunaga

发明人： Yasuhiko Matsunaga

IPC分类号： H04W40/00

CPC分类号： H04W28/08 ,  H04W16/18 ,  H04W24/02 ,  H04W88/12

摘要： A configuration of a wireless cell contained by a wireless network control station in a wireless access network is optimized to efficiently achieve leveling of a processing load in the wireless network control station. A wireless access network management device inputs input information including position information of a wireless cell, traffic demand of each wireless cell, location registration demand of each wireless cell, handover demand with respect to each adjacent wireless cells of each wireless cell, and internal processing time required by a wireless network control station for traffic processing, location registration processing, and handover processing. Then, a wireless cell group to be controlled by a wireless network control station is selected based on the input information so that processing loads of a plurality of wireless network control station are leveled.

摘要翻译： 对无线接入网络中的无线网络控制站所包含的无线小区的配置进行优化，以有效地实现无线网络控制站中的处理负载的调平。 无线接入网络管理设备输入包括无线小区的位置信息，每个无线小区的业务需求，每个无线小区的位置登记需求，相对于每个无线小区的每个相邻无线小区的切换需求的输入信息，以及内部处理时间 由无线网络控制站要求用于业务处理，位置注册处理和切换处理。 然后，基于输入信息选择要由无线网络控制站控制的无线小区组，使得多个无线网络控制站的处理负载被调平。

公开(公告)号：US07586786B2

公开(公告)日：2009-09-08

申请号：US12106953

申请日：2008-04-21

申请人： Yasuhiko Matsunaga ,  Fumitaka Arai ,  Makoto Sakuma ,  Tadashi Iguchi ,  Hisashi Watanobe ,  Hiroaki Tsunoda

发明人： Yasuhiko Matsunaga ,  Fumitaka Arai ,  Makoto Sakuma ,  Tadashi Iguchi ,  Hisashi Watanobe ,  Hiroaki Tsunoda

IPC分类号： G11C11/34

CPC分类号： H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

摘要： A method of reading out data from nonvolatile semiconductor memory including the steps of applying a first voltage to a bit line contact; applying a second voltage to a source line contact, wherein the second voltage is substantially smaller than the first voltage; applying a third voltage gates of third and fourth select gate transistors, the third voltage configured to bring the third and fourth select gate transistors into conduction; applying a fourth voltage to gates of the plurality of memory cell transistors of a second memory cell unit, the fourth voltage configured to bring the plurality of memory cell transistors of the second memory cell unit into conduction or not, depending on the data that is stored in the memory cell unit; and applying a fifth voltage to gates of the plurality of memory cell transistors of a first memory cell unit, the fifth voltage configured to bring the plurality of memory cell transistors of the first memory cell unit into conduction; wherein the fifth voltage is bigger than the fourth voltage.

摘要翻译： 一种从非易失性半导体存储器读出数据的方法，包括对位线接触施加第一电压的步骤; 向源极线接触施加第二电压，其中所述第二电压基本上小于所述第一电压; 施加第三和第四选择栅极晶体管的第三电压栅极，所述第三电压被配置为使所述第三和第四选择栅极晶体管导通; 对第二存储单元单元的多个存储单元晶体管的栅极施加第四电压，第四电压被配置为使第二存储单元单元的多个存储单元晶体管导通，取决于存储的数据 在存储单元中; 对第一存储单元单元的多个存储单元晶体管的栅极施加第五电压，第五电压被配置为使第一存储单元单元的多个存储单元晶体管导通; 其中所述第五电压大于所述第四电压。