公开(公告)号：US09293547B2

公开(公告)日：2016-03-22

申请号：US13237425

申请日：2011-09-20

申请人： Fumitaka Arai ,  Wataru Sakamoto ,  Fumie Kikushima ,  Hiroyuki Nitta

发明人： Fumitaka Arai ,  Wataru Sakamoto ,  Fumie Kikushima ,  Hiroyuki Nitta

IPC分类号： H01L29/788 ,  H01L21/28 ,  H01L29/792 ,  H01L29/423 ,  H01L21/764 ,  H01L27/115 ,  H01L29/66 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234

CPC分类号： H01L29/42336 ,  H01L21/76224 ,  H01L21/764 ,  H01L21/7682 ,  H01L21/823481 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7881

摘要： According to one embodiment, a part of a buried insulating film buried in a trench is removed; accordingly, an air gap is formed between adjacent floating gate electrodes in a word line direction, and the air gap is formed continuously along the trench in a manner of sinking below a control gate electrode.

摘要翻译： 根据一个实施例，去除埋在沟槽中的埋入绝缘膜的一部分; 因此，在字线方向上在相邻的浮置栅电极之间形成气隙，并且沿着沟槽以沉没在控制栅电极下方的方式连续地形成气隙。

公开(公告)号：US08829623B2

公开(公告)日：2014-09-09

申请号：US12248483

申请日：2008-10-09

申请人： Nobutoshi Aoki ,  Takashi Izumida ,  Masaki Kondo ,  Fumitaka Arai

发明人： Nobutoshi Aoki ,  Takashi Izumida ,  Masaki Kondo ,  Fumitaka Arai

IPC分类号： H01L27/088 ,  H01L27/115

CPC分类号： H01L27/11529 ,  H01L27/11524 ,  H01L27/11526

摘要： According to an aspect of the present invention, there is provided a semiconductor memory device including: a semiconductor substrate having: a contact region; a select gate region; and a memory cell region; a first element isolation region formed in the contact region and having a first depth; a second element isolation region formed in the select gate region and having a second depth; and a third element isolation region formed in the memory cell region and having a third depth which is smaller than the first depth.

摘要翻译： 根据本发明的一个方面，提供了一种半导体存储器件，包括：半导体衬底，具有：接触区域; 选择栅极区; 和存储单元区域; 形成在所述接触区域中并且具有第一深度的第一元件隔离区; 形成在所述选择栅极区中并具有第二深度的第二元件隔离区; 以及形成在所述存储单元区域中并且具有小于所述第一深度的第三深度的第三元件隔离区域。

公开(公告)号：US20130248968A1

公开(公告)日：2013-09-26

申请号：US13606757

申请日：2012-09-07

申请人： Satoshi NAGASHIMA ,  Fumitaka ARAI ,  Hisataka MEGURO

发明人： Satoshi NAGASHIMA ,  Fumitaka ARAI ,  Hisataka MEGURO

IPC分类号： H01L27/088 ,  H01L21/28

CPC分类号： H01L21/28273 ,  G11C16/0408 ,  H01L27/11524 ,  H01L27/11551 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

摘要： A nonvolatile semiconductor memory device a first memory cell array layer, a first insulation layer formed on top of the first memory cell array layer, a second memory cell array layer formed on the first insulation layer, and a control gate. The first and second memory cell array layers have first and second NAND cell units provided with multiple first and second memory cells connected in series in a first direction and the first and second selection gates connected at both ends of the multiple first and second memory cells. The control gate is formed via an insulation layer between gates of the memory cells on both sides thereof in the first direction, and extends in the second direction perpendicular to the first direction.

摘要翻译： 非易失性半导体存储器件，第一存储单元阵列层，形成在第一存储单元阵列层顶部的第一绝缘层，形成在第一绝缘层上的第二存储单元阵列层和控制栅极。 第一和第二存储单元阵列层具有第一和第二NAND单元单元，其具有在第一方向上串联连接的多个第一和第二存储单元，并且第一和第二选择栅极连接在多个第一和第二存储单元的两端。 控制栅极是通过在其第一方向的两侧的存储单元的栅极之间的绝缘层形成的，并且在垂直于第一方向的第二方向上延伸。

公开(公告)号：US08541830B1

公开(公告)日：2013-09-24

申请号：US13601468

申请日：2012-08-31

申请人： Satoshi Nagashima ,  Fumitaka Arai ,  Hisataka Meguro

发明人： Satoshi Nagashima ,  Fumitaka Arai ,  Hisataka Meguro

IPC分类号： H01L29/788 ,  H01L21/336 ,  G11C11/34

CPC分类号： H01L27/088 ,  H01L21/28273 ,  H01L27/11524 ,  H01L27/11551 ,  H01L29/788 ,  H01L29/7881

摘要： A nonvolatile semiconductor memory device according to an embodiment includes a plurality of cell array layers, each cell array layer including: a plurality of semiconductor layers that extends in a first direction; gate insulating layers; a plurality of floating gates arranged in the first direction; inter-gate insulating layers; and a plurality of control gates that extends in a second direction intersecting semiconductor layers, and faces the floating gates via the inter-gate insulating layers, in which, in the cell array layers adjacent each other in a stacking direction, the control gates of a lower cell array layer and the control gates of the an upper cell array layer are intersecting each other, and the floating gates within the lower cell array layer and the semiconductor layers within the upper cell array layer are aligned in position with each other.

摘要翻译： 根据实施例的非易失性半导体存储器件包括多个单元阵列层，每个单元阵列层包括：沿第一方向延伸的多个半导体层; 栅绝缘层; 沿所述第一方向布置的多个浮动栅极; 栅极间绝缘层; 以及多个控制栅极，其在与半导体层交叉的第二方向上延伸，并且经由所述栅极间绝缘层面向所述浮置栅极，其中，在层叠方向上彼此相邻的所述单元阵列层中，所述控制栅极 下单元阵列层和上单元阵列层的控制栅极彼此相交，并且下单元阵列层内的浮置栅极和上单元阵列层内的半导体层彼此对准。

公开(公告)号：US08377814B2

公开(公告)日：2013-02-19

申请号：US13164931

申请日：2011-06-21

申请人： Atsuhiro Sato ,  Hiroyuki Nitta ,  Fumitaka Arai

发明人： Atsuhiro Sato ,  Hiroyuki Nitta ,  Fumitaka Arai

IPC分类号： H01L21/28

CPC分类号： H01L27/11524 ,  H01L21/76816 ,  H01L27/11521

摘要： A semiconductor memory device includes a first block having first memory cells and first select transistors, a second block having second memory cells and second select transistors, and arranged adjacent to the first block in a first direction, the second select transistor being arranged to face the first select transistor and commonly having a diffusion region with the first select transistor, a first interconnection layer provided on the diffusion region between the first and second blocks and extending in a second direction, and a second interconnection layer having a first portion provided in contact with an upper portion of the first interconnection layer and extending to a portion outside the first interconnection layer, and a second portion extending in the second direction and connected to the first portion in a portion outside a portion on the first interconnection layer.

摘要翻译： 半导体存储器件包括具有第一存储器单元和第一选择晶体管的第一块，具有第二存储单元和第二选择晶体管的第二块，并且沿第一方向布置成与第一块相邻，第二选择晶体管被布置为面对 第一选择晶体管，并且通常具有与第一选择晶体管的扩散区，第一互连层，设置在第一和第二块之间的扩散区上并沿第二方向延伸;第二互连层，具有设置成与第一选择晶体管接触的第一部分 第一互连层的上部并且延伸到第一互连层外部的部分，以及第二部分，其在第二方向上延伸并且在第一互连层上的部分外部的部分连接到第一部分。

公开(公告)号：US08223558B2

公开(公告)日：2012-07-17

申请号：US13179714

申请日：2011-07-11

申请人： Tomoharu Tanaka ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Riichiro Shirota ,  Fumitaka Arai ,  Susumu Fujimura

发明人： Tomoharu Tanaka ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Riichiro Shirota ,  Fumitaka Arai ,  Susumu Fujimura

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/06

CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/345 ,  G11C16/3454 ,  G11C16/3459 ,  G11C16/3463 ,  G11C2211/5621

摘要： A NAND cell unit includes memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in an erase operation, is applied to all memory cells, thereby setting all memory cells out of an over-erased state. Thereafter, a program voltage of 20V is applied to the control gate of a selected memory cell, 0V is applied to the control gates of the two memory cells provided adjacent to the selected memory cell, and 11V is applied to the control gates of the remaining memory cells. Data is thereby programmed into the selected memory cell. The time for which the program voltage is applied to the selected memory cell is adjusted in accordance with the data to be programmed into the selected memory cell. Hence, data “0” can be correctly programmed into the selected memory cell, multi-value data can be read from any selected memory cell at high speed.

摘要翻译： NAND单元单元包括串联连接的存储单元。 对所有存储单元进行擦除操作。 然后，将与擦除操作中施加的擦除电压极性相反的软编程电压施加到所有存储单元，从而将所有存储单元设置为过擦除状态。 此后，将20V的编程电压施加到所选择的存储单元的控制栅极，将0V施加到与所选存储单元相邻设置的两个存储单元的控制栅极，并且将11V施加到其余的控制栅极 记忆细胞 因此数据被编程到所选择的存储单元中。 根据要编程到所选择的存储单元中的数据来调整对所选存储单元施加编程电压的时间。 因此，可以将数据“0”正确地编程到所选择的存储单元中，可以从任何选择的存储单元高速读取多值数据。

公开(公告)号：US20120126306A1

公开(公告)日：2012-05-24

申请号：US13238380

申请日：2011-09-21

申请人： Genki KAWAGUCHI ,  Fumitaka Arai ,  Satoshi Nagashima ,  Naoki Kai ,  Wataru Sakamoto ,  Hiroyuki Nitta

发明人： Genki KAWAGUCHI ,  Fumitaka Arai ,  Satoshi Nagashima ,  Naoki Kai ,  Wataru Sakamoto ,  Hiroyuki Nitta

IPC分类号： H01L29/788 ,  H01L21/28 ,  H01L29/792

CPC分类号： H01L27/11524 ,  H01L21/764 ,  H01L21/7682 ,  H01L27/11529 ,  H01L29/42376

摘要： According to one embodiment, a memory cell includes a charge storage layer. A first air gap is provided between charge storage layers adjacent in a word line direction. A second air gap is provided between charge storage layers adjacent in a bit line direction.

摘要翻译： 根据一个实施例，存储单元包括电荷存储层。 在字线方向相邻的电荷存储层之间设置第一气隙。 在位线方向相邻的电荷存储层之间提供第二气隙。

公开(公告)号：US20120069669A1

公开(公告)日：2012-03-22

申请号：US13237320

申请日：2011-09-20

申请人： Wataru SAKAMOTO ,  Fumitaka Arai

发明人： Wataru SAKAMOTO ,  Fumitaka Arai

IPC分类号： G11C16/10 ,  H01L21/762

CPC分类号： G11C16/0483 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/3418 ,  H01L21/28273 ,  H01L27/11524

摘要： A nonvolatile semiconductor storage device is disclosed. The device includes a cell group having a first memory cell and a second memory cell located first directionally adjacent to the first memory cell, and a programming circuit. The first memory cell is used for data retention and the second memory cell is used for adjustment of a threshold voltage of the first memory cell. The programming circuit is configured to program the first memory cell by applying voltage to the second memory cell to control the threshold voltage of the first memory cell to be higher than a first threshold voltage.

摘要翻译： 公开了一种非易失性半导体存储装置。 该设备包括具有第一存储器单元的单元组和位于第一定向相邻于第一存储单元的第二存储单元，以及编程电路。 第一存储单元用于数据保持，第二存储单元用于调整第一存储单元的阈值电压。 编程电路被配置为通过向第二存储器单元施加电压来对第一存储单元进行编程，以将第一存储单元的阈值电压控制为高于第一阈值电压。

公开(公告)号：US08120092B2

公开(公告)日：2012-02-21

申请号：US12565181

申请日：2009-09-23

申请人： Atsuhiro Sato ,  Fumitaka Arai

发明人： Atsuhiro Sato ,  Fumitaka Arai

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L27/11519 ,  H01L27/11521 ,  H01L27/11529

摘要： First gate electrodes of memory cell transistors are formed in series with each other on a semiconductor substrate. A second gate electrode of a first selection transistor is formed adjacent to one end of the first electrodes. A third gate electrode of a second selection transistor is formed adjacent to the second electrode. A fourth gate electrode of a peripheral transistor is formed on the substrate. First, second, and third sidewall films are formed on side surfaces of the second, third, and fourth gate electrodes, respectively. A film thickness of the third sidewall film is larger than that of the first and second sidewall films. A space between the first electrode and the second electrode is larger than a space between the first electrodes, and a space between the second electrode and the third electrode is larger than a space between the first electrode and the second electrode.

摘要翻译： 存储单元晶体管的第一栅电极在半导体衬底上彼此串联形成。 第一选择晶体管的第二栅电极与第一电极的一端相邻地形成。 第二选择晶体管的第三栅电极与第二电极相邻地形成。 在基板上形成周边晶体管的第四栅电极。 第一，第二和第三侧壁膜分别形成在第二，第三和第四栅电极的侧表面上。 第三侧壁膜的膜厚大于第一和第二侧壁膜的膜厚。 第一电极和第二电极之间的空间大于第一电极之间的空间，并且第二电极和第三电极之间的间隔大于第一电极和第二电极之间的间隔。

公开(公告)号：US08044448B2

公开(公告)日：2011-10-25

申请号：US12508904

申请日：2009-07-24

申请人： Takeshi Kamigaichi ,  Fumitaka Arai

发明人： Takeshi Kamigaichi ,  Fumitaka Arai

IPC分类号： H01L27/108

CPC分类号： H01L27/0207 ,  G11C5/025 ,  G11C5/063 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/1203

摘要： A nonvolatile semiconductor memory device includes: a memory cell array region having memory cells connected in series; a control circuit region disposed below the memory cell array region; and an interconnection portion electrically connecting the control circuit region and the memory cell array region. The memory cell array region includes: a plurality of first memory cell regions having the memory cells; and a plurality of connection regions. The interconnection portion is provided in the connection regions. The first memory cell regions are provided at a first pitch in a first direction orthogonal to a lamination direction of the memory cell array region and the control circuit region. The connection regions are provided between the first memory cell regions mutually adjacent in the first direction, and at a second pitch in a second direction orthogonal to the lamination direction and the first direction.

摘要翻译： 非易失性半导体存储器件包括：具有串联连接的存储单元的存储单元阵列区域; 设置在所述存储单元阵列区域下方的控制电路区域; 以及电连接控制电路区域和存储单元阵列区域的互连部分。 存储单元阵列区域包括：具有存储单元的多个第一存储单元区域; 和多个连接区域。 互连部分设置在连接区域中。 第一存储单元区域在与存储单元阵列区域和控制电路区域的层叠方向正交的第一方向上以第一间距设置。 连接区域设置在与第一方向相互相邻的第一存储单元区域和与层叠方向和第一方向正交的第二方向上的第二间距处。