公开(公告)号：US5864180A

公开(公告)日：1999-01-26

申请号：US28672

申请日：1998-02-24

申请人： Shizue Hori ,  Yoshiro Baba ,  Hiroyuki Sugaya ,  Hiroshi Naruse

发明人： Shizue Hori ,  Yoshiro Baba ,  Hiroyuki Sugaya ,  Hiroshi Naruse

IPC分类号： H01L21/205 ,  H01L21/20 ,  H01L29/04 ,  H01L21/36

CPC分类号： H01L21/2022 ,  H01L29/045 ,  Y10S257/923

摘要： A semiconductor device and a method for manufacturing the same, in which a leak current generated in a pn junction formed between a silicon substrate and an epitaxial layer can be reduced. A silicon oxide film is formed on a silicon substrate having a (100) crystal plane. The silicon oxide film is patterned to form an opened portion and an inclined surface on a pattern edge of the silicon oxide film. The inclined surface forms an angle of 54.74.+-.5.degree. with the silicon substrate. An epitaxial layer is formed in the opened portion by selective epitaxial growth.

摘要翻译： 可以减少在硅衬底和外延层之间形成的pn结中产生的漏电流的半导体器件及其制造方法。 在具有（100）晶面的硅衬底上形成氧化硅膜。 图案化氧化硅膜以在氧化硅膜的图案边缘上形成开口部分和倾斜表面。 倾斜表面与硅衬底形成54.74 +/- 5°的角度。 通过选择性外延生长在开口部分形成外延层。

公开(公告)号：US5282018A

公开(公告)日：1994-01-25

申请号：US53811

申请日：1993-04-29

申请人： Shunichi Hiraki ,  Yoshiro Baba

发明人： Shunichi Hiraki ,  Yoshiro Baba

IPC分类号： H01L21/74 ,  H01L27/088 ,  H01L29/423 ,  H01L29/739 ,  H01L29/78

CPC分类号： H01L29/7813 ,  H01L21/74 ,  H01L27/088 ,  H01L29/7397 ,  H01L29/4236

摘要： A power MOS semiconductor device, such as a vertical MOSFET, IGBT, and IPD, includes a body of semiconductor material having a first semiconductor layer having a first conductivity type, a second semiconductor layer having a second conductivity type and formed in the first semiconductor layer to provide a channel, a third semiconductor layer having the first conductivity type and formed in the second semiconductor layer, a trench formed in the first semiconductor layer across the third and second semiconductor layers, a gate insulating film covering a surface of the trench and extending to a surface of the third semiconductor layer, a gate electrode layer provided on the gate insulating film, and a buried layer having the first conductivity type provided in the first semiconductor layer so as to be contiguous to a bottom of the trench.

摘要翻译： 诸如垂直MOSFET，IGBT和IPD的功率MOS半导体器件包括具有第一导电类型的第一半导体层的半导体材料体，具有第二导电类型的第二半导体层，并形成在第一半导体层 为了提供通道，具有第一导电类型并形成在第二半导体层中的第三半导体层，形成在跨越第三和第二半导体层的第一半导体层中的沟槽，覆盖沟槽表面并延伸的栅绝缘膜 在所述第三半导体层的表面上设置设置在所述栅极绝缘膜上的栅电极层，以及设置在所述第一半导体层中以与所述沟槽的底部邻接的具有所述第一导电类型的掩埋层。

公开(公告)号：US06524894B1

公开(公告)日：2003-02-25

申请号：US09783303

申请日：2001-02-15

申请人： Hideki Nozaki ,  Yoshiro Baba ,  Motoshige Kobayashi

发明人： Hideki Nozaki ,  Yoshiro Baba ,  Motoshige Kobayashi

IPC分类号： H01L21332

CPC分类号： H01L29/0834 ,  H01L29/7395 ,  H01L29/7397

摘要： An N+ buffer layer formed on the underside of an N− layer includes an inactive region having incompletely activated ions and an active region having highly activated ions. The carrier concentration of the active region is higher than that of the inactive region. In the inactive region, the electrical activation rate X of the ions is expressed as 1%≦X≦30%. It is thus possible to achieve a PT structure using a Raw wafer, which reduces manufacturing costs and suppresses power consumption.

摘要翻译： 形成在N-层的下侧上的N +缓冲层包括具有不完全活化的离子的非活性区域和具有高活性离子的活性区域。 有源区的载流子浓度高于非活性区的载流子浓度。 在非活性区域中，离子的电活化速率X表示为1％<= X <= 30％。 因此，可以实现使用原始晶片的PT结构，这降低了制造成本并抑制了功耗。

公开(公告)号：US5917228A

公开(公告)日：1999-06-29

申请号：US800028

申请日：1997-02-13

申请人： Noboru Matsuda ,  Yoshiro Baba

发明人： Noboru Matsuda ,  Yoshiro Baba

IPC分类号： H01L21/329 ,  H01L29/47 ,  H01L29/861 ,  H01L29/872 ,  H01L31/107

CPC分类号： H01L29/66143 ,  H01L29/872

摘要： The present invention relates to a schottky-barrier diode capable of decreasing a leakage current due to damage generated on inner walls of trenches, and securing a large operation region for itself. In the device, an N.sup.- -type epitaxial layer is formed on a N.sup.+ -type silicon substrate. In a predetermined region in the epitaxial layer, a P.sup.+ -type base diffusion layer having high impurity concentration is formed. Trenches are formed through from the surface of the base diffusion layer to the epitaxial layer. In each of the trenches, an N.sup.- -type selective epitaxial growth region is formed. A schottky metal is formed on a surface comprising the surfaces of the base diffusion layer, which includes the selective epitaxial growth regions, and the epitaxial layer. Surface regions as the surfaces of the selective epitaxial growth regions filling the trenches function as diode operation regions.

摘要翻译： 本发明涉及一种肖特基势垒二极管，其能够减少由沟槽内壁产生的损伤引起的漏电流，并且可以确保其自身的大的操作区域。 在器件中，在N +型硅衬底上形成N型外延层。 在外延层的预定区域中，形成杂质浓度高的P +型基极扩散层。 沟槽形成为从基底扩散层的表面到外延层。 在每个沟槽中，形成N型选择性外延生长区。 在包括选择性外延生长区的基底扩散层的表面和外延层的表面上形成肖特基金属。 作为填充沟槽的选择性外延生长区域的表面的表面区域用作二极管操作区域。