公开(公告)号：US20060271799A1

公开(公告)日：2006-11-30

申请号：US11216018

申请日：2005-09-01

申请人： Shinichiro Shiratake ,  Yukihito Oowaki ,  Hiroyuki Hara ,  Tetsuya Fujita ,  Fumitoshi Hatori ,  Masataka Matsui

发明人： Shinichiro Shiratake ,  Yukihito Oowaki ,  Hiroyuki Hara ,  Tetsuya Fujita ,  Fumitoshi Hatori ,  Masataka Matsui

IPC分类号： G06F1/26

CPC分类号： G06F1/26 ,  G06F1/3203 ,  G06F1/3296 ,  Y02D10/172

摘要： According to the present invention, there is provided a semiconductor device comprising: a power supply circuit which receives an external power supply voltage supplied, and outputs an internal power supply voltage not higher than the external power supply voltage; a system module which receives the internal power supply voltage, and performs a predetermined operation; and a performance monitor circuit which measures a processing speed of said system module when the internal power supply voltage is applied, and, on the basis of the processing speed, outputs a first control signal which requests to set the external power supply voltage at a first level, and a second control signal which requests said power supply circuit to set the internal power supply voltage at a second level, wherein said power supply circuit outputs the internal power supply voltage having the second level on the basis of the second control signal applied thereto.

摘要翻译： 根据本发明，提供了一种半导体器件，包括：电源电路，接收所提供的外部电源电压，并输出不高于外部电源电压的内部电源电压; 接收内部电源电压并执行预定操作的系统模块; 以及性能监视电路，其在施加所述内部电源电压时测量所述系统模块的处理速度，并且基于所述处理速度，输出请求将所述外部电源电压设置为第一的第一控制信号 电平和第二控制信号，其请求所述电源电路将内部电源电压设定在第二电平，其中所述电源电路基于施加到其的第二控制信号输出具有第二电平的内部电源电压 。

公开(公告)号：US06643162B2

公开(公告)日：2003-11-04

申请号：US09799694

申请日：2001-03-07

申请人： Yoshiaki Takeuchi ,  Yukihito Oowaki

发明人： Yoshiaki Takeuchi ,  Yukihito Oowaki

IPC分类号： G11C1122

CPC分类号： G11C11/22

摘要： A ferroelectric memory has a memory cell array of memory cells having ferroelectric capacitors, which is divided into a plurality of blocks, a boost power circuit provided in each block of the memory cell array to generate a boost voltage required for operation of the memory, a boost power switch provided between a power line connected to an external power terminal and a power supply terminal of each boost power circuit, and remaining ON during normal operation of the memory, a voltage detector circuit for detecting a drop of voltage level of the power line, and a switch control circuit for turning off the boost power switches in the blocks of the memory cell array excluding the boost power switch in a currently selected block in response to the voltage detector circuit.

摘要翻译： 铁电存储器具有具有铁电电容器的存储单元阵列，其被分成多个块，设置在存储单元阵列的每个块中的升压功率电路，以产生存储器的操作所需的升压电压， 升压电源开关，其设置在连接到外部电源端子的电力线与每个升压电力电路的电源端子之间，并且在正常操作期间保持ON;电压检测器电路，用于检测电力线的电压水平的下降 以及开关控制电路，用于响应于电压检测器电路，关闭当前选择的块中除了升压功率开关之外的存储单元阵列的块中的升压功率开关。

公开(公告)号：US06545323B2

公开(公告)日：2003-04-08

申请号：US10014662

申请日：2001-12-14

申请人： Yukihito Oowaki ,  Masako Yoshida ,  Makoto Yoshimi

发明人： Yukihito Oowaki ,  Masako Yoshida ,  Makoto Yoshimi

IPC分类号： H01L2976

CPC分类号： G11C11/4091 ,  H01L27/10897 ,  H01L27/12

摘要： A semiconductor device includes a semiconductor layer used as a substrate formed on an insulating film, a plurality of MOS transistors arranged on the semiconductor layer and each having a gate, a source, and a drain, a pair of MOS transistors of the plurality of MOS transistors constituting a detection circuit for detecting magnitudes of potentials applied to the gates as a difference between conductances of the pair of transistors, and a diffusion layer region of the same conductivity type as that of the semiconductor layer, arranged on one of portions of the sources and drains of the pair of MOS transistors constituting the detection circuit, for connecting portions serving as the substrates of the pair of MOS transistors to each other.

摘要翻译： 半导体器件包括用作形成在绝缘膜上的衬底的半导体层，布置在半导体层上并且各自具有栅极，源极和漏极的多个MOS晶体管，多个MOS的一对MOS晶体管 构成检测电路的晶体管，用于检测施加到栅极的电位的大小，作为一对晶体管的电导率差，以及与半导体层的导电类型相同的导电类型的扩散层区域，布置在源的一部分 以及构成检测电路的一对MOS晶体管的漏极，用于将用作一对MOS晶体管的基板的部分彼此连接。

公开(公告)号：US06211686B1

公开(公告)日：2001-04-03

申请号：US09126133

申请日：1998-07-30

申请人： Kazuya Matsuzawa ,  Yukihito Oowaki

发明人： Kazuya Matsuzawa ,  Yukihito Oowaki

IPC分类号： G01R3126

CPC分类号： G01Q40/00 ,  H01L22/14 ,  H01L22/20 ,  Y10S977/854

摘要： The present invention comprises a SCM measuring apparatus and a control section. A control section adjusts shape data of a probe tip initially inputted based on SCM measurement for a standard specimen and a simulated result by the measuring apparatus, and then performs the SCM measurement by a standard specimen, and then on the basis of the measuring result, a impurity distribution is assumed. Next, the impurity distribution is adjusted so that the CV property calculated by the SCM simulation coincides with the CV property measured by the SCM measuring apparatus, and then the CV property is calculated again. The impurity distribution in case both of the CV properties coincide with each other is determined as a definitive impurity distribution. The definitive impurity distribution is outputted to a display apparatus, a printer, and so on. Therefore, it is possible to analyze the impurity distribution with accuracy smaller than a width of the probe tip.

摘要翻译： 本发明包括一个SCM测量装置和一个控制部分。 控制部根据标准样本的基于SCM测量的最初输入的探针尖端的形状数据和由测量装置的模拟结果进行调整，然后通过标准样本进行SCM测量，然后基于测量结果， 假定杂质分布。 接下来，调整杂质分布，使得通过SCM模拟计算的CV性质与由SCM测量装置测量的CV性质一致，然后再次计算CV性质。 在两种CV性质彼此一致的情况下的杂质分布被确定为确定的杂质分布。 确定的杂质分布被输出到显示装置，打印机等。 因此，可以精度小于探针尖端的宽度来分析杂质分布。

公开(公告)号：US06177811B1

公开(公告)日：2001-01-23

申请号：US09348623

申请日：1999-07-06

申请人： Tsuneaki Fuse ,  Yukihito Oowaki ,  Yoko Shuto

发明人： Tsuneaki Fuse ,  Yukihito Oowaki ,  Yoko Shuto

IPC分类号： H03K190944

CPC分类号： H03K19/215 ,  H01L27/1203 ,  H03K19/09441 ,  H03K19/0948

摘要： A semiconductor integrated circuit device includes a semiconductor substrate, a MOS transistor formed on the semiconductor substrate and having a first gate, wherein a first signal supplied to the first gate and a second signal supplied to a substrate region corresponding to the semiconductor substrate are combined with each other so that one logical signal is transmitted.

摘要翻译： 半导体集成电路器件包括半导体衬底，形成在半导体衬底上并具有第一栅极的MOS晶体管，其中提供给第一栅极的第一信号和提供给对应于半导体衬底的衬底区域的第二信号与 使得一个逻辑信号被发送。

公开(公告)号：US5831928A

公开(公告)日：1998-11-03

申请号：US744455

申请日：1996-11-07

申请人： Hiroaki Nakano ,  Takehiro Hasegawa ,  Yukihito Oowaki

发明人： Hiroaki Nakano ,  Takehiro Hasegawa ,  Yukihito Oowaki

IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C11/407 ,  G11C11/409 ,  G11C11/4096 ,  G11C8/00

CPC分类号： G11C7/10 ,  G11C11/4096

摘要： A semiconductor device includes a memory cell array having memory cells arranged in a matrix form, a plurality of bit lines for communicating information to the memory cells, and a plurality of word lines crossing the bit lines to select among the memory cells, a plurality of sense amplifiers for amplifying data read out onto the bit lines, a plurality of data lines for transferring data amplified by the sense amplifiers to the outside of the cell array, the plurality of data lines including first and second wiring layers, a plurality of column select circuits for controlling connections of the plurality of data lines and the plurality of sense amplifiers, and a plurality of control signal lines connected to the plurality of column select circuits, the plurality of control lines including third and fourth wiring layers.

摘要翻译： 半导体器件包括具有以矩阵形式布置的存储单元的存储单元阵列，用于向存储单元传送信息的多个位线以及与位线交叉的多条字线以便在存储单元之间进行选择， 用于放大读取到位线上的数据的读出放大器，用于将由读出放大器放大的数据传送到单元阵列外部的多条数据线，多条数据线包括第一和第二布线层，多列列选择 用于控制多个数据线和多个读出放大器的连接的电路以及连接到多个列选择电路的多个控制信号线，所述多个控制线包括第三和第四布线层。

公开(公告)号：US5590080A

公开(公告)日：1996-12-31

申请号：US527264

申请日：1995-09-12

申请人： Takehiro Hasagawa ,  Yukihito Oowaki

发明人： Takehiro Hasagawa ,  Yukihito Oowaki

IPC分类号： G11C11/409 ,  G11C11/405 ,  G11C11/4091 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C11/4091

摘要： A dynamic semiconductor memory device comprises a memory array by which memory-cell units having a plurality of dynamic type memory cells connected in series are arranged in a matrix. Sense-amplifier circuits compare and amplify potential difference of a pair of data lines connected to the memory-cell units. Sense amplifier drivers charge or discharge the data lines. The memory further comprises means for changing drive capacity of the sense amplifier driver during reading-out and either restoring or writing. For example, by making the restoring or writing drive capacity smaller than the reading drive capacity, electric charge or discharge peak currents of the data lines line can be reduced.

摘要翻译： 动态半导体存储器件包括存储器阵列，通过该存储器阵列将具有串联连接的多个动态型存储器单元的存储单元单元布置成矩阵。 感测放大器电路比较和放大连接到存储单元单元的一对数据线的电位差。 感应放大器驱动器对数据线充电或放电。 存储器还包括用于在读出和恢复或写入期间改变读出放大器驱动器的驱动能力的装置。 例如，通过使恢复或写入驱动能力小于读取驱动能力，可以减少数据线的电荷或放电峰值电流。

公开(公告)号：US5497351A

公开(公告)日：1996-03-05

申请号：US330120

申请日：1994-10-27

申请人： Yukihito Oowaki

发明人： Yukihito Oowaki

IPC分类号： G11C11/401 ,  G11C7/00 ,  G11C7/10 ,  G11C8/00

CPC分类号： G11C7/1042 ,  G11C7/10 ,  G11C7/1033 ,  G11C7/1039 ,  G11C7/1072

摘要： A dynamic random access memory with two divided memory banks is disclosed wherein memory cells are divided into first and second groups each of which includes an array of memory cells connected to a corresponding word line. Those memory cells are subdivided into subgroups each of which has four memory cells. A first set of input/output lines is provided for the first group of memory cells, and a second set of input/output lines is provided for the second group of memory cells. An output circuit section is connected to the those sets of input/output lines to output data transferred thereto. An access controller section specifies subgroups alternately from the first and second groups of memory cells with four memory cells as a substantial access minimum unit, accesses memory cells of a specified subgroup to read stored data therefrom and transfers the read data to corresponding input/output lines associated therewith. The read data is supplied to the output circuit section for conversion to serial data and then output therefrom.

公开(公告)号：US07236035B2

公开(公告)日：2007-06-26

申请号：US10990537

申请日：2004-11-18

申请人： Shinichiro Shiratake ,  Yukihito Oowaki ,  Fumitoshi Hatori ,  Mototsugu Hamada ,  Hiroyuki Hara

发明人： Shinichiro Shiratake ,  Yukihito Oowaki ,  Fumitoshi Hatori ,  Mototsugu Hamada ,  Hiroyuki Hara

IPC分类号： G06F1/04

CPC分类号： G06F1/10

摘要： A first logic circuit has its supply voltage controlled. A second logic circuit operates in response to an external clock signal. An adjustment circuit includes a first delay circuit supplied with the external clock signal, and a detection circuit which detects a skew between timing of a first clock signal output from the first logic circuit and a second clock signal output from the second logic circuit section. The adjustment circuit adjusts the delay time of the first delay circuit according to the result of the detection by the detection circuit and applies an output signal of the first delay circuit to the first logic circuit as a third clock signal.

摘要翻译： 第一个逻辑电路的电源电压被控制。 第二逻辑电路响应于外部时钟信号而工作。 调整电路包括提供有外部时钟信号的第一延迟电路和检测电路，其检测从第一逻辑电路输出的第一时钟信号的定时与从第二逻辑电路部分输出的第二时钟信号之间的偏差。 调整电路根据检测电路的检测结果来调整第一延迟电路的延迟时间，并将第一延迟电路的输出信号作为第三时钟信号施加到第一逻辑电路。

公开(公告)号：US06510071B2

公开(公告)日：2003-01-21

申请号：US09800912

申请日：2001-03-08

申请人： Yukihito Oowaki

发明人： Yukihito Oowaki

IPC分类号： G11C1122

CPC分类号： G11C7/20 ,  G11C11/22

摘要： A ferroelectric memory has a memory cell array having memory cells arrayed and each constructed of a ferroelectric capacitor and a transistor, a decode circuit configured to select the memory cells of the memory cell array; a sense amplifier circuit configured to detect and amplify data of a selected memory cell of the memory cell array selected by the decode circuit; and an access permission circuit configured to output an access permission signal for permitting an access to said memory cell array when a predetermined period elapses after switching ON a power source or after reaching a predetermined internal state.

摘要翻译： 铁电存储器具有存储单元阵列，存储单元排列并且由铁电电容器和晶体管构成，解码电路被配置为选择存储单元阵列的存储单元; 读出放大器电路，被配置为检测和放大由解码电路选择的存储单元阵列的选定存储单元的数据; 以及访问许可电路，被配置为当在接通电源之后或在达到预定的内部状态之后经过预定时间时，输出用于允许访问所述存储单元阵列的访问许可信号。