公开(公告)号：US5831928A

公开(公告)日：1998-11-03

申请号：US744455

申请日：1996-11-07

申请人： Hiroaki Nakano ,  Takehiro Hasegawa ,  Yukihito Oowaki

发明人： Hiroaki Nakano ,  Takehiro Hasegawa ,  Yukihito Oowaki

IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C11/407 ,  G11C11/409 ,  G11C11/4096 ,  G11C8/00

CPC分类号： G11C7/10 ,  G11C11/4096

摘要： A semiconductor device includes a memory cell array having memory cells arranged in a matrix form, a plurality of bit lines for communicating information to the memory cells, and a plurality of word lines crossing the bit lines to select among the memory cells, a plurality of sense amplifiers for amplifying data read out onto the bit lines, a plurality of data lines for transferring data amplified by the sense amplifiers to the outside of the cell array, the plurality of data lines including first and second wiring layers, a plurality of column select circuits for controlling connections of the plurality of data lines and the plurality of sense amplifiers, and a plurality of control signal lines connected to the plurality of column select circuits, the plurality of control lines including third and fourth wiring layers.

摘要翻译： 半导体器件包括具有以矩阵形式布置的存储单元的存储单元阵列，用于向存储单元传送信息的多个位线以及与位线交叉的多条字线以便在存储单元之间进行选择， 用于放大读取到位线上的数据的读出放大器，用于将由读出放大器放大的数据传送到单元阵列外部的多条数据线，多条数据线包括第一和第二布线层，多列列选择 用于控制多个数据线和多个读出放大器的连接的电路以及连接到多个列选择电路的多个控制信号线，所述多个控制线包括第三和第四布线层。

公开(公告)号：US5463577A

公开(公告)日：1995-10-31

申请号：US365104

申请日：1994-12-28

申请人： Yukihito Oowaki ,  Takehiro Hasegawa

发明人： Yukihito Oowaki ,  Takehiro Hasegawa

IPC分类号： G11C11/41 ,  G11C8/12 ,  G11C8/14 ,  G11C11/22 ,  G11C11/401 ,  G11C11/404 ,  G11C11/407 ,  G11C11/24

CPC分类号： G11C8/12 ,  G11C8/14

摘要： There is provided a semiconductor memory having a reduced power consumption in data access and a high access speed in a NAND cell array scheme in which a memory cell unit is constituted by cascade-connecting a plurality of memory cells with each other. A memory cell array is divided into a plurality of sub-arrays, and the divided sub-arrays are selectively activated, thereby decreasing the capacitances of the word lines, register word lines, bit lines, and the like which are charged/discharged in data access.

摘要翻译： 提供了一种在NAND单元阵列方案中数据访问中具有降低的功耗以及高存取速度的半导体存储器，其中通过将多个存储单元彼此级联连接而构成存储单元单元。 存储单元阵列被分成多个子阵列，并且分割的子阵列被选择性地激活，从而减少在数据中被充电/放电的字线，寄存器字线，位线等的电容 访问。

公开(公告)号：US5654912A

公开(公告)日：1997-08-05

申请号：US568500

申请日：1995-12-07

申请人： Takehiro Hasegawa ,  Yukihito Oowaki ,  Hitoshi Kuyama

发明人： Takehiro Hasegawa ,  Yukihito Oowaki ,  Hitoshi Kuyama

IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C11/404 ,  G11C11/405 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/24

CPC分类号： G11C11/4096 ,  G11C11/4045 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4091 ,  G11C7/103

摘要： A semiconductor memory device comprises a memory array in which word lines are driven by a single decoder or a plurality of memory arrays driven by a plurality of decoders operating with the same row address, in the memory array or memory arrays memory cell units in which a plurality of memory cells are connected in series being arranged in the form of an array, a plurality of sense amplifier arrays constituted by arranging a plurality of sense amplifiers each provided for a pair of bit lines or a plurality of pairs of bit lines to read out data from the memory cells of the memory cell arrays, the sense amplifier arrays being divided into a plurality of blocks, and the blocks corresponding to one memory cell array, a register array having a plurality of registers for storing data read out by the plurality of sense amplifiers, the register array being divided into a plurality of blocks, and the blocks corresponding to the sense amplifier block and one memory cell array, and a control circuit for independently controlling the blocks of the sense amplifier arrays and the register array and independently reading out data from the registers in the blocks.

摘要翻译： 半导体存储器件包括存储器阵列，其中字线由单个解码器驱动，或者由存储器阵列或存储器阵列存储单元单元中的由相同行地址操作的多个解码器驱动的多个存储器阵列驱动，其中， 多个存储单元以阵列的形式串联连接，多个读出放大器阵列通过布置多个读出放大器而构成，每个读出放大器分别设置用于一对位线或多对位线以读出 来自存储单元阵列的存储单元的数据，读出放大器阵列被划分为多个块，以及对应于一个存储单元阵列的块，具有多个寄存器的寄存器阵列，用于存储由多个块读出的数据 读出放大器，寄存器阵列被分成多个块，以及对应于读出放大器块和一个存储单元阵列的块，以及控制ci 用于独立控制读出放大器阵列和寄存器阵列的块，并独立地从块中的寄存器读出数据。

公开(公告)号：US5661678A

公开(公告)日：1997-08-26

申请号：US570966

申请日：1995-12-12

申请人： Masako Yoshida ,  Yukihito Oowaki ,  Takehiro Hasegawa ,  Kiyofumi Ochii ,  Masayuki Koizumi

发明人： Masako Yoshida ,  Yukihito Oowaki ,  Takehiro Hasegawa ,  Kiyofumi Ochii ,  Masayuki Koizumi

IPC分类号： H01L21/8242 ,  G11C11/404 ,  G11C11/405 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C11/404 ,  H01L27/108 ,  H01L27/10808 ,  H01L27/10829

摘要： A semiconductor memory device comprises a memory cell array including NAND type memory cell units arranged in matrix and having a plurality of dynamic type memory cells connected in series, a plurality of word lines, a plurality of bit lines arranged within the memory cell array, the plurality of bit lines including a bit line pairs which are arranged adjacent to each other or between which at least one bit line is interposed, and a plurality of sense amplifiers of a folded bit line type, provided in each of the plurality of bit line pairs, in which the memory cells are provided in positions corresponding to intersections of the bit lines and the word lines, and complementary data are written to two memory cells connected to each of the plurality of bit line pairs and one word line, and the two memory cells store one-bit data.

摘要翻译： 半导体存储器件包括存储单元阵列，其包括以矩阵形式布置的NAND型存储单元单元，并且具有串联连接的多个动态型存储单元，多个字线，布置在存储单元阵列内的多个位线， 多个位线包括彼此相邻布置或位于其中的至少一个位线之间布置的位线对以及设置在多个位线对中的每一个中的折叠位线类型的多个读出放大器 其中存储单元被提供在与位线和字线的交点对应的位置中，并且互补数据被写入连接到多个位线对和一个字线中的每一个的两个存储器单元，并且两个存储器 单元存储一位数据。

公开(公告)号：US5625602A

公开(公告)日：1997-04-29

申请号：US446291

申请日：1995-05-22

申请人： Takehiro Hasegawa ,  Yukihito Oowaki ,  Fujio Masuoka ,  Ryu Ogiwara ,  Shinichiro Shiratake ,  Shigeyoshi Watanabe

发明人： Takehiro Hasegawa ,  Yukihito Oowaki ,  Fujio Masuoka ,  Ryu Ogiwara ,  Shinichiro Shiratake ,  Shigeyoshi Watanabe

IPC分类号： G11C7/10 ,  G11C11/404 ,  G11C11/4096 ,  G11C11/4097 ,  G11C7/00

CPC分类号： G11C7/106 ,  G11C11/4045 ,  G11C11/4096 ,  G11C11/4097 ,  G11C7/1051 ,  G11C7/1078

摘要： A sense amplifier is connected between memory cell arrays, a re-writing register is arranged in position adjacent to the sense amplifier, transfer gates are disposed between the sense amplifier and the memory cell arrays, transfer gates are provided between bit lines of the memory cell arrays and global bit lines, and a gate control circuit for controlling the transfer gates is provided. When readout data is written into the register, the node of the sense amplifier is electrically separated from the bit lines and global bit lines.

摘要翻译： 读出放大器连接在存储单元阵列之间，重写寄存器布置在与读出放大器相邻的位置，传输门设置在读出放大器和存储单元阵列之间，传输门提供在存储单元的位线之间 阵列和全局位线，以及用于控制传输门的栅极控制电路。 当读出数据被写入寄存器时，读出放大器的节点与位线和全局位线电分离。

公开(公告)号：US5892724A

公开(公告)日：1999-04-06

申请号：US848152

申请日：1997-04-29

申请人： Takehiro Hasegawa ,  Yukihito Oowaki ,  Fujio Masuoka ,  Ryu Ogiwara ,  Shinichiro Shiratake ,  Shigeyoshi Watanabe

发明人： Takehiro Hasegawa ,  Yukihito Oowaki ,  Fujio Masuoka ,  Ryu Ogiwara ,  Shinichiro Shiratake ,  Shigeyoshi Watanabe

IPC分类号： G11C7/10 ,  G11C11/404 ,  G11C11/4096 ,  G11C11/4097 ,  G11C8/00

CPC分类号： G11C7/106 ,  G11C11/4045 ,  G11C11/4096 ,  G11C11/4097 ,  G11C7/1051 ,  G11C7/1078

摘要： A sense amplifier is connected between memory cell arrays, a re-writing register is arranged adjacent to the sense amplifier, first transfer gates are disposed between the sense amplifier and the memory cell arrays, second transfer gates are provided between bit lines of the memory cell arrays and global bit lines, and a gate control circuit for controlling the transfer gates is provided. When readout data is written into the register, the node of the sense amplifier is electrically separated from the bit lines and global bit lines.

摘要翻译： 读出放大器连接在存储单元阵列之间，重写寄存器与读出放大器相邻地布置，第一传输门设置在读出放大器和存储单元阵列之间，第二传输门提供在存储单元的位线之间 阵列和全局位线，以及用于控制传输门的栅极控制电路。 当读出数据被写入寄存器时，读出放大器的节点与位线和全局位线电分离。

公开(公告)号：US5717625A

公开(公告)日：1998-02-10

申请号：US784963

申请日：1997-01-16

申请人： Takehiro Hasegawa ,  Yukihito Oowaki ,  Shigeyoshi Watanabe ,  Ken-ichi Maeda ,  Mitsuo Saito ,  Masako Yoshida ,  Ryo Fukuda ,  Shinichiro Shiratake

发明人： Takehiro Hasegawa ,  Yukihito Oowaki ,  Shigeyoshi Watanabe ,  Ken-ichi Maeda ,  Mitsuo Saito ,  Masako Yoshida ,  Ryo Fukuda ,  Shinichiro Shiratake

IPC分类号： G11C8/08 ,  G11C11/404 ,  G11C15/00

CPC分类号： G11C8/08 ,  G11C11/4045

摘要： In a semiconductor memory device wherein a plurality of memory cell units formed by connecting a plurality of memory cells in series are provided and each of the memory cell units is connected to a bit line, the semiconductor memory device comprises control circuit for directly reading data of a register cell during a reading operation when the previous row address designates the same memory cell as the present row address, and a data changing controlling circuit for changing data of an arbitrary memory cell of the memory cell unit to data of the memory cell closest to the bit line contact in the memory cell unit, and a row decoder for corresponding row addresses which select the memory of memory cell units, to the upper addresses than the parts of the row addresses which select a memory unit among the memory cell units.

摘要翻译： 在其中提供通过串联连接多个存储单元而形成的多个存储单元单元的半导体存储器件中，并且每个存储单元单元连接到位线，该半导体存储器件包括用于直接读取数据的数据的控制电路 当前一行地址指定与当前行地址相同的存储单元时，读取操作期间的寄存器单元，以及数据改变控制电路，用于将存储单元单元的任意存储单元的数据改变为最靠近的存储单元的数据 存储单元单元中的位线接触，以及用于选择存储单元单元的存储器的相应行地址的行解码器，比存储单元单元中选择存储单元的行地址的部分高。

公开(公告)号：US20060271799A1

公开(公告)日：2006-11-30

申请号：US11216018

申请日：2005-09-01

申请人： Shinichiro Shiratake ,  Yukihito Oowaki ,  Hiroyuki Hara ,  Tetsuya Fujita ,  Fumitoshi Hatori ,  Masataka Matsui

发明人： Shinichiro Shiratake ,  Yukihito Oowaki ,  Hiroyuki Hara ,  Tetsuya Fujita ,  Fumitoshi Hatori ,  Masataka Matsui

IPC分类号： G06F1/26

CPC分类号： G06F1/26 ,  G06F1/3203 ,  G06F1/3296 ,  Y02D10/172

摘要： According to the present invention, there is provided a semiconductor device comprising: a power supply circuit which receives an external power supply voltage supplied, and outputs an internal power supply voltage not higher than the external power supply voltage; a system module which receives the internal power supply voltage, and performs a predetermined operation; and a performance monitor circuit which measures a processing speed of said system module when the internal power supply voltage is applied, and, on the basis of the processing speed, outputs a first control signal which requests to set the external power supply voltage at a first level, and a second control signal which requests said power supply circuit to set the internal power supply voltage at a second level, wherein said power supply circuit outputs the internal power supply voltage having the second level on the basis of the second control signal applied thereto.

摘要翻译： 根据本发明，提供了一种半导体器件，包括：电源电路，接收所提供的外部电源电压，并输出不高于外部电源电压的内部电源电压; 接收内部电源电压并执行预定操作的系统模块; 以及性能监视电路，其在施加所述内部电源电压时测量所述系统模块的处理速度，并且基于所述处理速度，输出请求将所述外部电源电压设置为第一的第一控制信号 电平和第二控制信号，其请求所述电源电路将内部电源电压设定在第二电平，其中所述电源电路基于施加到其的第二控制信号输出具有第二电平的内部电源电压 。

公开(公告)号：US07057917B2

公开(公告)日：2006-06-06

申请号：US10743906

申请日：2003-12-24

申请人： Ryu Ogiwara ,  Daisaburo Takashima ,  Sumio Tanaka ,  Yukihito Oowaki ,  Yoshiaki Takeuchi

发明人： Ryu Ogiwara ,  Daisaburo Takashima ,  Sumio Tanaka ,  Yukihito Oowaki ,  Yoshiaki Takeuchi

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： A chain type ferroelectric random access memory has a memory cell unit including ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier. A value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.

摘要翻译： 链式铁电随机存取存储器具有包括彼此串联电连接的铁电存储单元的存储单元单元，连接到存储单元单元的电极的板线，连接到存储单元单元的另一个电极的位线 通过开关晶体管，放大该位线及其互补位线的电压的读出放大器，以及插在开关晶体管和读出放大器之间的晶体管。 作为板线电压和比较放大的升压期间获得的晶体管中的栅极电压的最小值的值小于在板线掉电期间获得的晶体管中的栅极电压的最大值 电压和比较放大。 利用这些特征，存储单元中的累积电荷的减小减少，并且在读/写操作期间阻止了干扰的发生。

公开(公告)号：US06643162B2

公开(公告)日：2003-11-04

申请号：US09799694

申请日：2001-03-07

申请人： Yoshiaki Takeuchi ,  Yukihito Oowaki

发明人： Yoshiaki Takeuchi ,  Yukihito Oowaki

IPC分类号： G11C1122

CPC分类号： G11C11/22

摘要： A ferroelectric memory has a memory cell array of memory cells having ferroelectric capacitors, which is divided into a plurality of blocks, a boost power circuit provided in each block of the memory cell array to generate a boost voltage required for operation of the memory, a boost power switch provided between a power line connected to an external power terminal and a power supply terminal of each boost power circuit, and remaining ON during normal operation of the memory, a voltage detector circuit for detecting a drop of voltage level of the power line, and a switch control circuit for turning off the boost power switches in the blocks of the memory cell array excluding the boost power switch in a currently selected block in response to the voltage detector circuit.

摘要翻译： 铁电存储器具有具有铁电电容器的存储单元阵列，其被分成多个块，设置在存储单元阵列的每个块中的升压功率电路，以产生存储器的操作所需的升压电压， 升压电源开关，其设置在连接到外部电源端子的电力线与每个升压电力电路的电源端子之间，并且在正常操作期间保持ON;电压检测器电路，用于检测电力线的电压水平的下降 以及开关控制电路，用于响应于电压检测器电路，关闭当前选择的块中除了升压功率开关之外的存储单元阵列的块中的升压功率开关。