Simulation vector generation from HDL descriptions for observability-enhanced statement coverage
    32.
    发明授权
    Simulation vector generation from HDL descriptions for observability-enhanced statement coverage 有权
    来自HDL描述的模拟向量生成可观察性增强语句覆盖

    公开(公告)号:US06816825B1

    公开(公告)日:2004-11-09

    申请号:US09335755

    申请日:1999-06-18

    CPC classification number: G01R31/318307 G01R31/318364

    Abstract: A method of automatically generating vector sequences for an observability based coverage metric supports design validation. A design validation method for Register Transfer Level (RTL) circuits includes the generation of a tag list. Each tag in the tag list models an error at a location in HDL code at which a variable is assigned a value. Interacting linear and Boolean constraints are generated for the tag, and the set of constraints is solved using an HSAT solver to provide a vector that covers the tag. For each generated vector, tag simulation is performed to determine which others of the tags in the tag list are also covered by that vector. Vectors are generated until all tags have been covered, if possible within predetermined time constraints, thus automatically providing a set of vectors which will propagate errors in the HDL code to an observable output. Performance of the design validation method is enhanced through various heuristics involving path selection and tag magnitude maximization.

    Abstract translation: 自动生成基于可观察性的覆盖度量向量序列的方法支持设计验证。 寄存器传输级(RTL)电路的设计验证方法包括生成标签列表。 标签列表中的每个标签在HDL代码中的变量分配了一个值的位置处模拟错误。 为标签生成交互线性和布尔约束,并使用HSAT求解器解决约束集,以提供覆盖标签的向量。 对于每个生成的矢量,执行标签模拟以确定标签列表中哪些标签中的哪些标签也被该向量覆盖。 如果可能的话在预定的时间限制内,直到所有标签被覆盖为止,才产生向量,从而自动地提供将HDL代码中的错误传播到可观察输出的一组向量。 通过涉及路径选择和标签幅度最大化的各种启发式方法,提高了设计验证方法的性能。

    Non-networked RFID-PUF authentication
    35.
    发明授权
    Non-networked RFID-PUF authentication 有权
    非网络化RFID-PUF认证

    公开(公告)号:US08683210B2

    公开(公告)日:2014-03-25

    申请号:US12623045

    申请日:2009-11-20

    Inventor: Srinivas Devadas

    CPC classification number: H04L9/3278 H04L2209/805

    Abstract: An integrated circuit includes a sequence generator configured to generate a series of challenges; a hidden output generator configured to generate a series of hidden outputs, each hidden output a function of a corresponding challenge in the series of challenges; and bit reduction circuitry configured to generate a response sequence including a plurality of response parts, each response part a function of a corresponding plurality of hidden outputs.

    Abstract translation: 集成电路包括被配置为产生一系列挑战的序列发生器; 隐藏的输出发生器被配置为产生一系列隐藏的输出,每个隐藏的输出都是一系列挑战中的相应挑战的功能; 以及比特缩减电路,被配置为生成包括多个响应部分的响应序列,每个响应部分是对应的多个隐藏输出的功能。

    CRYPTOGRAPHIC SECURITY USING FUZZY CREDENTIALS FOR DEVICE AND SERVER COMMUNICATIONS
    36.
    发明申请
    CRYPTOGRAPHIC SECURITY USING FUZZY CREDENTIALS FOR DEVICE AND SERVER COMMUNICATIONS 有权
    使用FUZZY证书进行设备和服务器通信的CRYPTOGRAPHIC SECURITY

    公开(公告)号:US20130010957A1

    公开(公告)日:2013-01-10

    申请号:US13543295

    申请日:2012-07-06

    CPC classification number: H04L9/3278 H04L9/0844 H04L9/0866

    Abstract: An approach to cryptographic security uses a “fuzzy” credential, in contrast to a “hard” credential, to eliminate cryptographic algorithmic repeatability on a device that may be subject to physical attacks. By eliminating repeatability performed at an algorithmic (e.g., gate or software) level, a device inherently lacks one of the fundamental setup assumptions associated with certain classes of side channel, fault injection, timing, and related attacks, thus helps to protect the system against such attacks while preserving the cryptographic security of the system.

    Abstract translation: 加密安全性的方法使用与硬凭证相反的模糊凭证来消除可能遭受物理攻击的设备上的加密算法重复性。 通过消除在算法(例如门或软件)级别执行的重复性,设备固有地缺乏与某些类别的侧信道,故障注入,定时和相关攻击相关联的基本设置假设之一,从而有助于保护系统免受 这种攻击同时保留了系统的加密安全性。

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