公开(公告)号：US20050041290A1

公开(公告)日：2005-02-24

申请号：US10866418

申请日：2004-06-11

申请人： Tengda Du ,  Kevin Zhang

发明人： Tengda Du ,  Kevin Zhang

IPC分类号： G02B6/34 ,  H04J14/02 ,  H04Q11/00 ,  G02B6/00 ,  G02B5/30 ,  G02B27/28

CPC分类号： H04J14/02 ,  G02B6/272 ,  G02B6/29302 ,  G02B6/29386 ,  H04Q11/0005 ,  H04Q2011/0009 ,  H04Q2011/0015 ,  H04Q2011/0016 ,  H04Q2011/0026 ,  H04Q2011/0075

摘要： An optical interleaver for use in a range of telecommunications applications including optical multiplexers/demultiplexers and optical routers. The optical device includes an optical processing loop which allows multi-stage performance characteristics to be achieved with a single physical filtration stage. Optical processing on the first leg and second legs of the loop is asymmetrical thereby improving the integrity of the optical signals by effecting complementary chromatic dispersion on the first and second legs. A fundamental filter cell within the interleaver filters optical signals propagating on each of the two legs of the optical loop which intersects the fundamental filter cell.

摘要翻译： 一种用于包括光复用器/解复用器和光路由器的电信应用范围内的光交织器。 光学装置包括光学处理回路，其允许通过单个物理过滤级来实现多级性能特性。 在环路的第一腿部和第二腿部上的光学处理是不对称的，从而通过在第一和第二腿部上实现互补色散而提高光学信号的完整性。 交织器内的基本滤波器单元滤波在与基波滤波器单元相交的光环路的两个支路上传播的光信号。

公开(公告)号：US06850364B2

公开(公告)日：2005-02-01

申请号：US10170055

申请日：2002-06-12

申请人： Ping Xie ,  R. Brad Bettman ,  Haisheng Rong ,  Kevin Zhang ,  Yalan Mao ,  Wei Wang ,  Simon Yuanxiang Wu

发明人： Ping Xie ,  R. Brad Bettman ,  Haisheng Rong ,  Kevin Zhang ,  Yalan Mao ,  Wei Wang ,  Simon Yuanxiang Wu

IPC分类号： G02B6/34 ,  H04J14/02 ,  H04Q11/00 ,  G02B5/30

CPC分类号： G02B6/272 ,  G02B6/29352 ,  H04J14/02 ,  H04Q11/0005 ,  H04Q2011/0009 ,  H04Q2011/0015 ,  H04Q2011/0016 ,  H04Q2011/0026 ,  H04Q2011/0075

摘要： An optical device that can be used in a range of telecommunications applications including optical multiplexers/demultiplexers and optical routers. The optical device includes an optical processing loop which allows multi-stage performance characteristics to be achieved with a single physical filtration stage. Optical processing on the first leg and second legs of the loop is asymmetrical thereby improving the integrity of the optical signals by effecting complementary chromatic dispersion on the first and second legs. In an embodiment of the invention the optical device includes a fundamental filter cell, a retro reflector and a splitter/combiner. The fundamental filter cell filters optical signals propagating on each of two legs of an optical loop which intersects the fundamental filter cell. The fundamental filter cell operates as a full waveplate to the odd set of channels and a half waveplate to the even set of channels on a selected one of the two legs and as a half waveplate to the odd set of channels and a full waveplate to the even set of channels on a remaining one of the two legs. The retro reflector optically couples with the fundamental filter cell to reflect the optical signals from one of the two legs to an other of the two legs to form the optical loop. The splitter/combiner optically couples between the fundamental filter cell and the retro reflector to split or combine the odd set of channels and the even set of channels depending on the propagation direction of the optical signals along the optical loop.

摘要翻译： 可用于包括光复用器/解复用器和光路由器在内的一系列电信应用中的光学装置。 光学装置包括光学处理回路，其允许通过单个物理过滤级来实现多级性能特性。 在环路的第一腿部和第二腿部上的光学处理是不对称的，从而通过在第一和第二腿部上实现互补色散而提高光学信号的完整性。 在本发明的一个实施例中，光学装置包括基本滤波器单元，回射反射器和分离器/组合器。 基本滤波器单元滤波在与基波滤波器单元相交的光环路的两条支路上传播的光信号。 基本滤波器单元作为完整波片操作到奇数通道组，并且将半波片作用到两个选定的一个通道上的偶数通道组，以及半波片到奇数通道组，并将完整波片作为 甚至在两条腿中剩下的一条通道上设置通道。 后向反射器与基本滤波器单元光学耦合以将来自两个腿中的一个的光学信号反射到两个腿中的另一个，以形成光学环路。 分路器/组合器在基本滤波器单元和回射反射器之间光耦合，以根据沿着光学环路的光信号的传播方向将奇数组信道和偶数组信道分离或组合。

公开(公告)号：US06621954B1

公开(公告)日：2003-09-16

申请号：US09713634

申请日：2000-11-14

申请人： Ping Xie ,  Kevin Zhang ,  Robert Burn, III

发明人： Ping Xie ,  Kevin Zhang ,  Robert Burn, III

IPC分类号： G02B632

CPC分类号： G02B6/2937

摘要： A portion of an optical device is disclosed. In one aspect of the present invention, the device comprises a cylinder formed about an axis having first and second ends, the second end being formed so as to define a segment of an inward-facing concave spherical surface. A module is provided defining a cylinder formed about the axis and having first and second ends and an optical element disposed therein about the axis. The first end of the module is formed so as to define a segment of an outward-facing convex spherical surface, and the convex surface is complimentary in shape to the concave surface. The complimentary concave and convex surfaces of the cylinder and the module are mated so as to allow the optical element to be aligned about a plane forming a predetermined angle with the axis.

摘要翻译： 公开了一种光学装置的一部分。 在本发明的一个方面中，所述装置包括围绕具有第一和第二端的轴线形成的圆柱体，所述第二端部形成为限定向内凹的球形表面的一段。 提供模块，其限定围绕轴线形成的圆柱体，并且具有第一和第二端部以及围绕轴线设置在其中的光学元件。 模块的第一端形成为限定向外凸的球形表面的一段，并且凸形表面在凹形表面上互补。 气缸和模块的互补的凹凸表面配合，以允许光学元件围绕与轴线形成预定角度的平面对齐。

公开(公告)号：US5986923A

公开(公告)日：1999-11-16

申请号：US73670

申请日：1998-05-06

申请人： Kevin Zhang ,  Donald R. Weiss

发明人： Kevin Zhang ,  Donald R. Weiss

IPC分类号： G11C11/41 ,  G11C11/412 ,  G11C11/00

CPC分类号： G11C11/412

摘要： A single-ended SRAM cell design reduces SRAM size and provides high storage cell noise margin. A virtual ground line is coupled to the source of the driver NFET of each I/O port inverter of each storage cell in a common bitline column. An isolation mechanism couples the virtual ground line to a low reference voltage during reads and during a write of a "0" to a storage cell, and isolates the virtual ground line from the low reference voltage during a write of a "1" to a storage cell. A clamping device is coupled to the virtual ground line to prevent the potential on the virtual ground line from exceeding the threshold voltage of the isolation mechanism and flipping the stored value in any of the other commonly coupled storage cells when a "1" is being written to another of the commonly coupled storage cells.

摘要翻译： 单端SRAM单元设计减少了SRAM大小，并提供了高的存储单元噪声容限。 虚拟接地线在公共位线列中耦合到每个存储单元的每个I / O端口反相器的驱动器NFET的源极。 隔离机构在读取期间和在向存储单元写入“0”期间将虚拟接地线耦合到低参考电压，并且在写入“1”期间将虚拟接地线与低参考电压隔离 存储单元。 夹紧装置耦合到虚拟接地线，以防止虚拟接地线上的电位超过隔离机构的阈值电压，并且当写入“1”时将存储的值翻转到任何其他共同耦合的存储单元中 到另一个共同耦合的存储单元。

公开(公告)号：US5949256A

公开(公告)日：1999-09-07

申请号：US961844

申请日：1997-10-31

申请人： Kevin Zhang ,  Jenny R. Carman

发明人： Kevin Zhang ,  Jenny R. Carman

IPC分类号： G11C17/18 ,  G11C7/06 ,  G11C11/409 ,  G11C11/419 ,  G11C16/06

CPC分类号： G11C7/065

摘要： An asymmetric sense amplifier is disclosed for use with single-ended memory arrays. The sense amplifier has a bit input, a reference input, an enable input, and bistable output circuitry. The reference input may simply be tied to V.sub.DD. The bistable output circuitry includes first and second output nodes disposed between first and second pull-up/pull-down paths, respectively. The first pull-up and pull-down paths may include first pull-up and pull-down FET channels, respectively. The second pull-up and pull-down paths may include second pull-up and pull-down FET channels, respectively. The bistable output circuitry is operable to be stable in first and second states. In both states, the output nodes are at opposite potentials. The sense amplifier is asymmetrical in the following sense: Either the second pull-down FET channel is wider than the first pull-down FET channel, or the first pull-up FET channel is wider than the second pull-up FET channel, or both. The result of the asymmetry is that the bistable output circuitry has a bias toward stabilizing in its first state. When the voltage on the bit input is equal to the voltage on the reference input and the enable input is asserted, the bistable output circuitry stabilizes in its first state; but when the voltage on the bit input is less than the voltage on the reference input by more than a threshold amount and the enable input is asserted, the bias is overcome and the bistable output circuitry stabilizes in its second state.

摘要翻译： 公开了一种用于单端存储器阵列的非对称读出放大器。 读出放大器具有位输入，参考输入，使能输入和双稳态输出电路。 参考输入可以简单地连接到VDD。 双稳态输出电路包括分别设置在第一和第二上拉/下拉路径之间的第一和第二输出节点。 第一上拉和下拉路径可以分别包括第一上拉和下拉FET通道。 第二上拉和下拉路径可以分别包括第二上拉和下拉FET通道。 双稳态输出电路可操作以在第一和第二状态下稳定。 在这两种状态下，输出节点处于相反的电位。 感测放大器在以下意义上是不对称的：第二下拉FET通道比第一下拉FET通道宽，或第一上拉FET通道比第二上拉FET通道宽，或两者均为 。 不对称的结果是双稳态输出电路具有在其第一状态下稳定的偏向。 当位输入上的电压等于参考输入上的电压并且使能输入被置位时，双稳态输出电路稳定在其第一状态; 但是当位输入上的电压小于参考输入上的电压超过阈值并且使能输入被断言时，该偏压被克服，并且双稳态输出电路稳定在其第二状态。

公开(公告)号：US07660498B2

公开(公告)日：2010-02-09

申请号：US12103365

申请日：2008-04-15

申请人： Kevin Zhang ,  Guojun Lai ,  Youjian Wu ,  Fahua Lan

发明人： Kevin Zhang ,  Guojun Lai ,  Youjian Wu ,  Fahua Lan

IPC分类号： G02B6/32

CPC分类号： G02B6/327 ,  G02B6/14

摘要： A glass optical reflective tap is described that optically connects two optical fibers and may tap a portion of the light that is being communicated between the optical fibers. In one embodiment of the invention, the optical filter includes two D-lenses that operate as focusing or collimator lenses. The first D-lens focuses an optical signal onto a tap filter that allows a majority of the light within an optical signal to pass and also reflects a small portion of optical signal light to a reflective port. The second D-lens focuses the passed light into a transmission port of an optical fiber.

摘要翻译： 描述了玻璃光学反射抽头，其光学地连接两根光纤并且可以抽出正在光纤之间连通的一部分光。 在本发明的一个实施例中，滤光器包括作为聚焦或准直透镜操作的两个D透镜。 第一个D透镜将光信号聚焦到抽头滤波器上，允许光信号内的大部分光通过，并将一小部分光信号光反射到反射端口。 第二个D镜头将通过的光线聚焦到光纤的传输端口。

公开(公告)号：US07561766B2

公开(公告)日：2009-07-14

申请号：US11753499

申请日：2007-05-24

申请人： Johhny Zhong ,  Yin Zhang ,  Steve Wang ,  Ping Xie ,  Kevin Zhang

发明人： Johhny Zhong ,  Yin Zhang ,  Steve Wang ,  Ping Xie ,  Kevin Zhang

IPC分类号： G02B6/26 ,  G02B6/42 ,  G02B6/32

CPC分类号： G02B6/2937 ,  G02B6/29386 ,  H04J14/02

摘要： A thin film interleaver device is disclosed. The thin film interleaver includes thin film optics. The thin film(s) are formed such that they reflect one group of wavelengths while allowing a second group of wavelengths to pass through the thin film(s). The thin film(s) exhibit a flat top frequency response across the channel bandwidths of the multiplexed signal for which the thin film filter is designed such that the thin film interleaver is less sensitive to wavelength drift and temperature variations.

摘要翻译： 公开了一种薄膜交织器件。 薄膜交织器包括薄膜光学器件。 薄膜形成为使得它们反射一组波长，同时允许第二组波长穿过薄膜。 该薄膜在多路复用信号的通道带宽上表现出平坦的顶频响应，薄膜滤波器被设计成使得薄膜交织器对波长漂移和温度变化较不敏感。

公开(公告)号：US07177176B2

公开(公告)日：2007-02-13

申请号：US10883609

申请日：2004-06-30

申请人： Bo Zheng ,  Kevin Zhang ,  Fatih Hamzaoglu ,  Yih (Eric) Wang

发明人： Bo Zheng ,  Kevin Zhang ,  Fatih Hamzaoglu ,  Yih (Eric) Wang

IPC分类号： G11C11/00 ,  G11C5/14 ,  G11C7/10

CPC分类号： G11C11/417 ,  G11C11/412

摘要： In embodiments of the present invention, a static random access memory (SRAM) device has an array of memory cells in columns and rows. An individual memory cell includes two PMOS pull-up devices coupled to two NMOS pull-down devices. In READ mode and/or STANDBY/NO-OP mode of a column, the two PMOS pull-up devices are effectively strengthened by forward biasing the PMOS n-wells or by utilizing a lower threshold voltage PMOS device by implanting a lower halo dose in the PMOS device. In WRITE mode of a column, the two PMOS pull-up devices are effectively weakened by reverse biasing the PMOS n-wells or by coupling the sources of the NMOS devices to virtual ground (VSSi).

摘要翻译： 在本发明的实施例中，静态随机存取存储器（SRAM）装置具有列和行中的存储器单元阵列。 单个存储单元包括耦合到两个NMOS下拉器件的两个PMOS上拉器件。 在列的READ模式和/或STANDBY / NO-OP模式下，通过正向偏置PMOS n阱或利用较低阈值电压PMOS器件，通过将较低的光晕剂量 PMOS器件。 在列的写入模式下，通过反向偏置PMOS n阱或通过将NMOS器件的源耦合到虚拟接地（V SUB SSi），两个PMOS上拉器件被有效地削弱。

公开(公告)号：US07079426B2

公开(公告)日：2006-07-18

申请号：US10950740

申请日：2004-09-27

申请人： Kevin Zhang ,  Fatih Hamzaoglu ,  Lin Ma

发明人： Kevin Zhang ,  Fatih Hamzaoglu ,  Lin Ma

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C5/14 ,  G11C11/413

摘要： A dynamic multi-voltage memory array features SRAM cells that are subjected to different biasing conditions, depending on the operating mode of the cells. The selected SRAM cell receives a first voltage when a read operation is performed, and receives a second voltage when a write operation is performed. By biasing the cell differently for the two distinct operations, a total decoupling of the read and write operations is achieved. The disclosed memory array, as well as future SRAM designs incorporating the multi-voltage capability thus avoid the conflicting requirements of read and write operations. Random single-bit failures of the memory array are reduced, due to the improvement in read stability and write margin.

公开(公告)号：US06862207B2

公开(公告)日：2005-03-01

申请号：US10271500

申请日：2002-10-15

申请人： Liqiong Wei ,  Kevin Zhang

发明人： Liqiong Wei ,  Kevin Zhang

IPC分类号： G11C11/419 ,  G11C11/00 ,  G11C8/00

CPC分类号： G11C11/419

摘要： A method and apparatus for a four transistor SRAM comprising an array or block of cells. Each cell comprises a pair of pass transistors and a pair of pull-down transistors. In one embodiment of the invention, when the SRAM block is in a standby mode, the difference between the voltage at the gate and the voltage at the source of each pass transistor is greater than 0, and less than the threshold voltage of the pass transistor. In one embodiment of the invention a ground connection of the memory cell is switched such that when the SRAM block is in the standby mode, the ground connection is a virtual ground connection and when the SRAM block is in an active mode the ground connection is a global ground connection.