Methods and circuitry for implementing first-in first-out structure
    421.
    发明授权
    Methods and circuitry for implementing first-in first-out structure 有权
    实现先进先出结构的方法和电路

    公开(公告)号:US06963220B2

    公开(公告)日:2005-11-08

    申请号:US10749965

    申请日:2003-12-31

    CPC classification number: G06F5/10 G06F2205/106

    Abstract: Methods and circuitry for implementing high speed first-in first-out (FIFO) structures. In one embodiment, a FIFO is disclosed that allows the frequency of one clock, e.g., the write clock, to be different than (e.g., half) that of the other (read) clock. In another embodiment a FIFO is presented that can be set and/or reset asynchronously. Other embodiments are disclosed wherein the read and write pointers are effectively monitored to ensure proper timing relationship, to detect loss of clock as well as to detect other abnormal FIFO conditions.

    Abstract translation: 用于实现高速先进先出(FIFO)结构的方法和电路。 在一个实施例中,公开了允许一个时钟(例如写时钟)的频率与另一(读取)时钟的频率不同的(例如,一半)的FIFO。 在另一个实施例中,呈现可以异步地设置和/或复位的FIFO。 公开了其他实施例,其中有效地监视读取和写入指针,以确保正确的时序关系,以检测时钟损耗以及检测其他异常FIFO条件。

    Intermediate layout for resolution enhancement in semiconductor fabrication
    422.
    发明申请
    Intermediate layout for resolution enhancement in semiconductor fabrication 有权
    用于半导体制造中分辨率增强的中间布局

    公开(公告)号:US20050229131A1

    公开(公告)日:2005-10-13

    申请号:US11074882

    申请日:2005-03-07

    CPC classification number: G06F17/5068 G03F1/36

    Abstract: Intermediate resolution-enhancement state layouts are generated based upon an original non-resolution enhanced layout of an integrated circuit and an associated resolution-enhanced layout. The intermediate resolution-enhancement state layout includes fragments corresponding to parts of the original layout and biases associated with the fragments, where the biases indicate distances between the fragments and the resolution-enhanced layout. The fragments are also assigned attributes such as fragment type, fragment location, and biases. The intermediate resolution-enhancement state layouts can be combined to generate the layout for a full chip IC. Two or more intermediate resolution-enhancement state layouts are assembled and are locally reconverged to adjust the resolution enhancement associated with the intermediate resolution-enhancement state layouts and obtain the intermediate resolution-enhancement state layouts for the full IC.

    Abstract translation: 基于集成电路的原始非分辨率增强布局和相关联的分辨率增强布局来生成中间分辨率增强状态布局。 中间分辨率增强状态布局包括对应于原始布局的部分和与片段相关联的偏移的片段,其中偏置指示片段之间的距离和分辨率增强布局。 片段还被分配了诸如片段类型,片段位置和偏差等属性。 中间分辨率增强状态布局可以组合以产生全芯片IC的布局。 组合两个或更多个中间分辨率增强状态布局并且被局部再变换以调整与中间分辨率增强状态布局相关联的分辨率增强,并获得用于全部IC的中间分辨率增强状态布局。

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