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461.发明授权公开(公告)号：US11735119B2
公开(公告)日：2023-08-22
申请号：US17750804
申请日：2022-05-23
Inventor： Zhidong Yuan , Yongqian Li , Can Yuan
IPC: G09G3/32 , G09G3/3266 , G11C19/28 , G09G3/3233
CPC classification number: G09G3/3266 , G11C19/28 , G09G3/3233 , G09G2310/0286 , G09G2310/061 , G09G2310/08
Abstract: A shift register unit and a control method thereof, a gate driving circuit and a control method thereof, and a display apparatus are provided. The shift register unit includes: a first shift register coupled to an input signal terminal, a first clock signal terminal and a second clock signal terminal. The first shift register is configured to generate a first output signal based on the signal at the first clock signal terminal and generate a second output signal based on the signal at the second clock signal terminal; and a second shift register coupled to the input signal terminal and a third clock signal terminal, the second shift register is configured to generate a third output signal based on the signal at the third clock signal terminal. The first shift register includes a first control circuit, a first output circuit and a second output circuit.
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公开(公告)号：US11705047B2
公开(公告)日：2023-07-18
申请号：US17721234
申请日：2022-04-14
Inventor： Xuehuan Feng , Yongqian Li , Xing Zhang
IPC: G09G3/20
CPC classification number: G09G3/2092 , G09G2310/0286 , G09G2310/061 , G09G2310/08
Abstract: A shift-register unit includes a first circuit including a first input circuit coupled via a first node to a first output circuit, and a second circuit including a second input circuit coupled via a second node to a second output circuit. The first input circuit is configured to control a voltage level of the first node in response to a first input signal. The first output circuit is configured to output a shift-register signal and a first output signal in response to the voltage level of the first node. The second input circuit is configured to control a voltage level of the second node in response to the first input signal. The second output circuit is configured to output a second output signal in response to the voltage level of the second node. The first input circuit and the second input circuit have a same circuit structure.
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公开(公告)号：US11699382B2
公开(公告)日：2023-07-11
申请号：US17780626
申请日：2021-07-21
Inventor： Xuehuan Feng , Xing Yao , Jingbo Xu , Xuelian Cheng
IPC: G09G3/3266 , G09G3/20
CPC classification number: G09G3/2074 , G09G3/3266 , G09G2300/0443 , G09G2310/061 , G09G2310/08 , G09G2320/0257
Abstract: Provided is a method for driving a display device including n rows of sub-pixels; the method includes: driving the first frame of image, including: performing normal display driving on the n rows of sub-pixels in a display driving period, performing darkness insertion driving on a rows, from the 1st to ath rows, of sub-pixels in a first darkness insertion sub-period, and performing darkness insertion driving on (n−a) rows, from the (a+1)th to nth rows, of sub-pixels in a second darkness insertion sub-period driving a second frame of image, including: performing normal display driving on the n rows of sub-pixels in a display driving period, performing darkness insertion driving on b rows, from the 1st to bth rows, of sub-pixels in a first darkness insertion sub-period, and performing darkness insertion driving on (n−b) rows, from the (b+1)th to nth rows, of sub-pixels in a second darkness insertion sub-period.
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公开(公告)号：US20230196994A1
公开(公告)日：2023-06-22
申请号：US18108730
申请日：2023-02-13
Inventor： Xuehuan FENG , Yongqian LI , Hao LIU
IPC: G09G3/3225 , G11C19/28 , G09G3/3266
CPC classification number: G09G3/3225 , G11C19/28 , G09G3/3266 , G09G2310/0286
Abstract: A shift register unit, a gate driving circuit, a display device, and a driving method are disclosed. The shift register unit includes a first sub-circuit, a second sub-circuit, a leakage prevention circuit and a blanking input sub-circuit, wherein the first sub-circuit comprises a first input circuit and a first output circuit; the second sub-circuit comprises a second input circuit and a second output circuit; the leakage prevention circuit is configured to control a level of a leakage prevention node under control of the level of the first node, so as to turn off a circuit connected between the first node and the leakage prevention node; and the blanking input sub-circuit is connected to the first node and the second node, and is configured to receive a selection control signal and a first clock signal, and control the level of the first node and the level of the second node.
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公开(公告)号：US20230157111A1
公开(公告)日：2023-05-18
申请号：US17795950
申请日：2021-09-28
Inventor： Pan Xu , Zhidong Yuan
IPC: H10K59/131 , G09G3/3233 , H10K59/122
CPC classification number: H10K59/1315 , G09G3/3233 , H10K59/122 , G09G2300/0842 , G09G2300/0819 , G09G2300/0426
Abstract: A display substrate is provided. The display substrate includes: a base substrate including a display area and a peripheral area located on at least a first side of the display area; a plurality of pixel units arranged in an array along a first direction and a second direction in the display area of the base substrate, where the pixel units include a pixel driver circuit and a light-emitting device electrically connected to the pixel driver circuit, and the light-emitting device includes a cathode, an anode, and a light-emitting layer disposed between the cathode and the anode; and a cathode line located in the peripheral area and electrically connected to the cathode. The cathode line substantially surrounds the display area and is electrically connected to the cathode line at a plurality of positions. The cathode line includes a first cathode sub-line located in the same layer as the anode.
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Patent Agency Ranking
公开(公告)号：US20230154410A1
公开(公告)日：2023-05-18
申请号：US17642983
申请日：2020-10-23
Inventor： Xuehuan FENG , Yongqian LI
IPC: G09G3/3266 , G09G3/3233 , H10K59/131 , G11C19/28
CPC classification number: G09G3/3266 , G09G3/3233 , H10K59/131 , G11C19/28 , G09G2310/0286 , G09G2300/0426 , G09G2300/0842 , G09G2330/021
Abstract: A display panel includes a plurality of rows of sub-pixels and at least one gate driver circuit that are disposed on a base substrate. Each sub-pixel includes a pixel driver circuit and a light-emitting device coupled to the pixel driver circuit, and a gate driver circuit includes a plurality of shift registers that are cascaded and a plurality of control signal lines. A shift register is coupled to a plurality of pixel driver circuits in at least one row of sub-pixels and at least a part of the plurality of control signal lines, and includes a plurality of first thin film transistors that are divided into a plurality of first thin film transistors. At least one thin film transistor group is located in the display region and distributed between adjacent sub-pixels in a same row of sub-pixels.
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467.发明申请公开(公告)号：US20230125979A1
公开(公告)日：2023-04-27
申请号：US18077269
申请日：2022-12-08
Inventor： Xuehuan FENG , Pan XU
Abstract: The present disclosure relates to the field of display technology, and in particular, to a gate driving structure, an array substrate and a display device. The gate driving structure may include: a base substrate; a shift register, formed on the base substrate, and including a plurality of thin film transistors and at least one capacitor, the capacitor being coupled to the thin film transistor; and a signal wiring group, formed on the base substrate, and including a plurality of signal wirings spaced apart from each other, the signal wiring being coupled to the thin film transistor. An orthographic projection of the capacitor on the base substrate is at least partially overlapped with an orthographic projection of the signal wiring group on the base substrate.
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公开(公告)号：US11615743B2
公开(公告)日：2023-03-28
申请号：US17490054
申请日：2021-09-30
Inventor： Xuehuan Feng , Yongqian Li , Hao Liu
IPC: G09G3/3225 , G09G3/3266 , G11C19/28
Abstract: A shift register unit, a gate driving circuit, a display device, and a driving method are disclosed. The shift register unit includes a first sub-circuit, a second sub-circuit, and a leakage prevention circuit. The first sub-circuit includes a first input circuit and a first output circuit, the first input circuit is configured to control a level of a first node in response to a first input signal. The second sub-circuit includes a second input circuit and the second output circuit. The leakage prevention circuit is connected to the first node, and is configured to control a level of the leakage prevention node under control of the level of the first node, so that a circuit connected between the first node and the leakage prevention node is turned off, and a circuit connected between the second node and the leakage prevention node is turned off.
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公开(公告)号：US20230084070A1
公开(公告)日：2023-03-16
申请号：US17770250
申请日：2021-04-15
Inventor： Xuehuan FENG , Yongqian LI
Abstract: The present disclosure provides a shift register unit, a signal generation unit circuit, a driving method and a display device. The shift register unit includes a first node control circuit, a second node control circuit and an output circuit, the first node control circuit is used to control a potential of a first node; the second node control circuit controls a potential of a second node; the output circuit is used to control and maintain the potential of the first node and the potential of the second node, and control to connect the output terminal and the second clock signal terminal under the control of the potential of the first node, and control to connect the input terminal and the second voltage terminal under the control of the potential of the second node.
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公开(公告)号：US20230033702A1
公开(公告)日：2023-02-02
申请号：US17791558
申请日：2020-12-23
Inventor： Xuehuan FENG , Yongqian LI
IPC: G09G3/3266
Abstract: A display panel (100), comprising: a substrate (1), a plurality of sub-pixels (2) and a gate driving circuit (3). The sub-pixels (2) comprise pixel driving circuits (21). The gate driving circuit (3) comprises multiple stages of cascaded shift registers (31), wherein one stage of shift registers (31) is electrically connected to a plurality of pixel driving circuits (21) in one row of sub-pixels (2). The gate driving circuit (3) further comprises: a plurality of cascaded input signal lines (34) and a plurality of cascaded display reset signal lines (35). Each cascaded input signal line (34) is configured to be connected to a shift signal end (CR ) of one stage of shift registers (31) and an input signal end (Iput) of another stage of shift registers (31); and each cascaded display reset signal line (35) is configured to be connected to the shift signal end (CR ) of one stage of shift registers (31) and a display reset signal end (STD) of another stage of shift registers. The display panel (100) is provided with a plurality of sub-pixel regions (S) used for arranging the plurality of sub-pixels (2), and first gap regions (D) located between two adjacent columns of sub-pixel regions (5); and the cascaded display reset signal lines (35) and the cascaded input signal lines (34) are both arranged in the first gap regions (D), and the two are arranged in different first gap regions (D).
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