Multiplexing circuitry, multiplexing method, multiplexing module, and display device

    公开(公告)号:US11929022B2

    公开(公告)日:2024-03-12

    申请号:US17641991

    申请日:2021-05-18

    IPC分类号: G09G3/3225

    摘要: The present disclosure provides a multiplexing circuitry, a multiplexing method, a multiplexing module, and a display device. The multiplexing circuitry includes N multiplexing unit circuitries, N energy storage unit circuitries and N control unit circuitries. An nth multiplexing unit circuitry is configured to enable an nth output data line to be electrically coupled to or electrically decoupled from an input data line under the control of a potential at an nth control end; an nth energy storage unit circuitry is configured to control a potential at the nth control end in accordance with an nth clock signal; and an nth control unit circuitry is configured to enable the nth control end to be electrically coupled to or electrically decoupled from an nth switch control line in accordance with a control voltage signal and an nth switch control signal.

    Array substrate and manufacturing method thereof, and display device

    公开(公告)号:US11508295B2

    公开(公告)日:2022-11-22

    申请号:US17309360

    申请日:2020-08-12

    IPC分类号: G09G3/3225 G11C19/28

    摘要: An array substrate and a manufacturing method thereof, and a display device are provided. The array substrate includes: a base substrate, and a GOA circuit, a source electrode IC and PLG wires arranged on the base substrate, and the PLG wires connect the GOA circuit with the source electrode IC. The GOA circuit transmits a GOA signal, and the GOA signal comprises a cascade signal and a non-cascade signal. The PLG wires comprise a first PLG wire group and at least one second PLG wire group, the first PLG wire group transmits the cascade signal, the second PLG wire group transmits the non-cascade signal, a line width of the first PLG wire group is smaller than that of the second PLG wire group, and the first PLG wire group is located at a side of the second PLG wire group distal to an active area of the base substrate.

    Display substrate, display apparatus, and method of fabricating display substrate

    公开(公告)号:US11482688B2

    公开(公告)日:2022-10-25

    申请号:US16762985

    申请日:2019-07-05

    IPC分类号: H01L51/52 H01L27/32 H01L51/56

    摘要: A display substrate including a plurality of light emitting elements respectively in a plurality of subpixels configured to emit light for image display is provided. A respective one of the plurality of subpixels includes a base substrate; a first auxiliary cathode; a passivation layer; a first insulating layer; a second auxiliary cathode; a second insulating layer; and a pixel definition layer. The display substrate has a cathode aperture extending through the pixel definition layer and an auxiliary cathode aperture extending through the first insulating layer and the passivation layer. A cathode of a respective one of the plurality of light emitting elements extends into the cathode aperture to electrically connect with the second auxiliary cathode. The second auxiliary cathode extends into the auxiliary cathode aperture to electrically connect with the first auxiliary cathode.

    Shift register, driving method thereof, gate drive circuit, array substrate and display device

    公开(公告)号:US11250784B2

    公开(公告)日:2022-02-15

    申请号:US16642469

    申请日:2019-07-29

    IPC分类号: G09G3/3266 G11C19/28

    摘要: The present disclosure discloses a shift register, a driving method thereof, a gate drive circuit, an array substrate and a display device. With a signal control circuit, a branch control circuit, a cascade signal output circuit and at least two scan signal output circuits, each shift register can output at least two scan signals to correspond to different gate lines in a display panel. This can reduce the number of shift registers in a gate drive circuit and the space occupied by the gate drive circuit and can achieve an ultra-narrow frame design, as compared with an existing shift register that can only output one scan signal. Moreover, as signals of different output control node do not influence each other, the output stability can also be improved.

    ARRAY SUBSTRATE, DISPLAY APPARATUS, METHOD OF FABRICATING ARRAY SUBSTRATE, AND PIXEL DRIVING CIRCUIT

    公开(公告)号:US20210408160A1

    公开(公告)日:2021-12-30

    申请号:US16963346

    申请日:2019-09-27

    IPC分类号: H01L27/32 G09G3/3225

    摘要: An array substrate includes an array of a plurality of subpixels including a plurality of columns of subpixels respectively spaced apart by a plurality of inter-subpixel regions; a plurality of pixel driving circuits respectively driving light emission of the plurality of subpixels; and a plurality of detection and compensation lead lines respectively configured to respectively detect signals in the plurality of subpixels and respectively compensate signals in the plurality of subpixels. A respective one of a plurality of detection and compensation lead lines is disposed in a first inter-subpixel region between two directly adjacent columns of subpixels. The respective one of the plurality of detection and compensation lead lines is spaced apart by at least one columns of subpixels from a signal line configured to transmit an alternating current and arranged along a direction parallel to the respective one of the plurality of detection and compensation lead lines.

    SHIFT REGISTER UNIT, DRIVING METHOD, GATE DRIVING CIRCUIT, AND DISPLAY DEVICE

    公开(公告)号:US20210233476A1

    公开(公告)日:2021-07-29

    申请号:US17256049

    申请日:2020-02-12

    IPC分类号: G09G3/3266 G11C19/28

    摘要: A shift register unit, a driving method, a gate driving circuit, and a display device are disclosed. The shift register unit includes: a shift circuit, used to output, to a first output end during a first time period, a power control signal, and output the power control signal to a second output end during a second time period; and a signal integrated circuit, used to output the power control signal to a third output end in response to the power control signal and a first output signal, output the power control signal to the third output end in response to the power control signal and a second output signal, and output, to the third output end at times other than the first and second time period in response to the power control signal, the first output signal and the second output signal, a first pull-down power signal.