公开(公告)号：US06839888B2

公开(公告)日：2005-01-04

申请号：US10407100

申请日：2003-04-03

Applicant: Vidyabhusan Gupta

Inventor： Vidyabhusan Gupta

IPC: G06F15/78 ,  H03K19/00

CPC classification number: G06F15/7867

Abstract: There is disclosed a field programmable gate array (FPGA) that performs bit swapping functions in the interconnects rather than in the configurable logic blocks of the FPGA. The FPGA comprises: 1) a plurality of configurable logic blocks, including a first CLB having an N-bit output and a second CLB having an N-bit input; 2) a plurality of interconnects; 3) a plurality of interconnect switches for coupling ones of the plurality of interconnects to each other and to inputs and outputs of the plurality of configurable logic blocks; and 4) an interconnect switch controller for controlling the plurality of interconnect switches, wherein the interconnect switch controller in a first switch configuration causes a firsts group of interconnects coupled to the N-bit output of the first CLB to be coupled to a second group of interconnects coupled to the N-bit input of the second CLB according to a first connection mapping and wherein the interconnect switch controller in a second switch configuration causes the first group of interconnects to be coupled to the second group of interconnects according to a second connection mapping.

Abstract translation: 公开了一种现场可编程门阵列（FPGA），其在互连中而不是FPGA的可配置逻辑块中执行位交换功能。 FPGA包括：1）多个可配置逻辑块，包括具有N位输出的第一CLB和具有N位输入的第二CLB; 2）多个互连; 3）多个互连开关，用于将所述多个互连中的一个互连到所述多个可配置逻辑块的输入和输出; 以及4）用于控制所述多个互连开关的互连开关控制器，其中所述第一开关配置中的所述互连开关控制器使得耦合到所述第一CLB的N位输出的第一组互连耦合到第二组 互连，其根据第一连接映射耦合到第二CLB的N位输入，并且其中第二交换机配置中的互连开关控制器根据第二连接映射使第一组互连耦合到第二组互连 。

公开(公告)号：US06839355B1

公开(公告)日：2005-01-04

申请号：US09461672

申请日：1999-12-14

Applicant: Bernard Saby ,  Harry Hvostov ,  Anthony Fung ,  Peter Groz

Inventor： Bernard Saby ,  Harry Hvostov ,  Anthony Fung ,  Peter Groz

IPC: H04L29/10 ,  H04L12/28 ,  H04L12/56 ,  H04L12/66

CPC classification number: H04L12/4625 ,  H04L12/2801

Abstract: A cable modem link layer bridge includes a downstream forwarding task and an upstream forwarding task. The downstream forwarding task is structured to receive a first message from a cable network and forward the first message to a customer premises equipment (CPE). The upstream forwarding task is structured to receive a second message from the CPE and forward the second message to the cable network, the upstream and downstream forwarding tasks being multitasked such that the second message is forwarded by the upstream forward task while the first message is being forwarded by the downstream forwarding task.

Abstract translation: 电缆调制解调器链路层桥接器包括下游转发任务和上游转发任务。 下游转发任务被构造成从有线网络接收第一消息并将第一消息转发到客户驻地设备（CPE）。 上游转发任务被构造成从CPE接收第二消息并将第二消息转发到有线网络，上游和下游转发任务是多任务的，使得第二消息由第一消息正在被上游转发任务转发 由下游转发任务转发。

公开(公告)号：US20040263264A1

公开(公告)日：2004-12-30

申请号：US10603238

申请日：2003-06-24

Applicant: STMicroelectronics, Inc.

Inventor： Rong Yin ,  Mehdi Zamanian

IPC: H03B001/00

CPC classification number: H03B5/36 ,  H03B5/06

Abstract: A method and circuit are disclosed for enabling an oscillator circuit to oscillate a predetermined period of time following completion of a power-up operation. The circuit may include a counter having a control for receiving a control signal from a system power-on-reset circuit, and a clock input. A ring oscillator has an output coupled to the clock input of the counter.

Abstract translation: 公开了一种方法和电路，用于使振荡器电路能够在上电操作完成之后的预定时间段内振荡。 电路可以包括具有用于从系统上电复位电路接收控制信号的控制器和时钟输入的计数器。 环形振荡器具有耦合到计数器的时钟输入的输出。

公开(公告)号：US20040225799A1

公开(公告)日：2004-11-11

申请号：US10434821

申请日：2003-05-09

Applicant: STMicroelectronics, Inc.

Inventor： Taylor J. Leaming

IPC: H05K007/10 ,  G06F013/00

CPC classification number: G06K19/07

Abstract: An integrated circuit for a smart card may include a transceiver and a controller for cooperating with the transceiver to receive operating requests from a host device. The controller may perform smart card operations based upon respective operating requests. Moreover, the controller also may cooperate with the transceiver to receive at least one advance request from the host device to indicate that at least one operating request will follow. By way of example, the standby operation may include loading data in at least one buffer, which may be sent to the host device based upon receiving the at least one operating request. Other standby operations may include disabling data transmission to the host device, such as when the communications bus of the host device is preoccupied, and ceasing performing a current smart card operation to allow a higher priority smart card operation to be performed, for example.

Abstract translation: 用于智能卡的集成电路可以包括收发器和用于与收发器协作以从主机设备接收操作请求的控制器。 控制器可以基于相应的操作请求执行智能卡操作。 此外，控制器还可以与收发器协作以从主机设备接收至少一个提前请求，以指示至少一个操作请求将遵循。 作为示例，备用操作可以包括在至少一个缓冲器中加载数据，其可以基于接收到至少一个操作请求而被发送到主机设备。 其他备用操作可以包括例如当主机设备的通信总线被占用时停止向主机设备的数据传输，并停止执行当前的智能卡操作以允许执行更高优先级的智能卡操作。

公开(公告)号：US20040196391A1

公开(公告)日：2004-10-07

申请号：US10407505

申请日：2003-04-04

Applicant: STMicroelectronics, Inc.

Inventor： George Q. Chen ,  Li Hong ,  Peter McGuinness

IPC: H04N005/262

CPC classification number: G06K9/209 ,  G06T5/003 ,  G06T5/50 ,  G06T15/20 ,  G06T2207/10028 ,  H04N5/2258 ,  H04N5/23229

Abstract: A compound camera system comprising component cameras that generate image data of an object and a processor that receives first image data from a first component camera and second image data from a second component camera and generates a virtual image. The processor projects virtual pixel data (u,v) to generate point data (x,y,z) located at depth, znullZ1, of a object plane of the object and projects the said point data (x,y,z) to generate first pixel data (u1,v1) located at a image plane of the first image. The processor also projects said point data (x,y,z) located at the depth, znullZ1, of the said object plane to generate second pixel data (u2,v2) located at the second image. The processor generates the virtual image by combining the color of first pixel data (u1,v1) and the color of second pixel data (u2,v2)

Abstract translation: 一种复合照相机系统，包括产生对象的图像数据的组件相机和从第一组件相机接收第一图像数据的处理器和来自第二组件相机的第二图像数据，并生成虚拟图像。 处理器投影虚拟像素数据（u，v）以生成位于物体的物平面深度z = Z1处的点数据（x，y，z），并投影所述点数据（x，y，z） 以产生位于第一图像的像平面处的第一像素数据（u1，v1）。 处理器还投影位于所述物体平面的深度z = Z1处的所述点数据（x，y，z），以产生位于第二图像处的第二像素数据（u2，v2）。 处理器通过组合第一像素数据（u1，v1）的颜色和第二像素数据（u2，v2）的颜色来生成虚拟图像，

公开(公告)号：US20040196067A1

公开(公告)日：2004-10-07

申请号：US10249353

申请日：2003-04-02

Applicant: STMICROELECTRONICS, INC.

Inventor： Razak Hossain ,  Marco Cavalli

IPC: H03K019/20

CPC classification number: H03K3/356156 ,  H03K3/0375

Abstract: A testable, pulse-triggered static flip-flop. A pulse generator produces a data enable trigger pulse only when a test enable input is low, and a scan test enable trigger pulse only when a test enable input is high. The data enable trigger pulse controls the data input to the flip-flop, while the scan test enable trigger pulse controls the scan test input to the flip-flop. The flip-flop consists of a selection circuit comprised of two latches, each including an inverter and a transmission gate. One latch receives the data input and the other latch receives the scan test input. The data enable trigger pulse controls the transmission gate receiving the data input, and the scan test trigger pulse controls the transmission gate receiving the scan test input. The flip-flop also includes a keeper circuit consisting of a feedback inverter and a static latch.

Abstract translation: 可测试的脉冲触发静态触发器。 只有当测试使能输入为低电平时，脉冲发生器才产生数据使能触发脉冲，只有当测试使能输入为高电平时，扫描测试才能使能触发脉冲。 数据使能触发脉冲控制触发器输入的数据，而扫描测试使能触发脉冲控制触发器的扫描测试输入。 触发器由包括两个锁存器的选择电路组成，每个锁存器包括反相器和传输门。 一个锁存器接收数据输入，另一个锁存器接收扫描测试输入。 数据使能触发脉冲控制传输门接收数据输入，扫描测试触发脉冲控制传输门接收扫描测试输入。 触发器还包括由反馈逆变器和静态锁存器组成的保持器电路。

公开(公告)号：US20040158807A1

公开(公告)日：2004-08-12

申请号：US10248721

申请日：2003-02-12

Applicant: STMICROELECTRONICS, INC.

Inventor： Razak Hossain ,  Fabrizio Viglione ,  Bernard Bourgin

IPC: G06F017/50

CPC classification number: G06F17/505

Abstract: A method for synthesizing a domino logic circuit design (18) from a source circuit definition (14) using a static logic circuit synthesis tool (12) includes generating a preliminary domino logic circuit (26) design using the circuit synthesis tool (12) and optimizing an attribute of the preliminary domino logic circuit design by substituting a static cell design for a domino cell design having a same function in the preliminary domino logic circuit design (30).

Abstract translation: 使用静态逻辑电路合成工具（12）从源电路定义（14）合成多米诺逻辑电路设计（18）的方法包括使用电路合成工具（12）生成初步的多米诺逻辑电路（26）设计，以及 通过将静态单元设计替换为在初级多米诺逻辑电路设计中具有相同功能的多米诺骨牌单元设计来优化初步多米诺逻辑电路设计的属性（30）。

公开(公告)号：US20040150443A1

公开(公告)日：2004-08-05

申请号：US10761760

申请日：2004-01-21

Applicant: STMicroelectronics, Inc.

Inventor： Srikanth R. Muroor

IPC: H03L007/06

CPC classification number: H03L7/099 ,  H03K3/0231

Abstract: There is disclosed a voltage controlled oscillator (VCO) that receives nullV(IN) and nullV(IN) control voltages and outputs a VCO output signal having an oscillation frequency determined by the nullV(IN) and nullV(IN) control voltages. The VCO comprises: 1) a storage capacitor charged linearly by a constant charge current and discharged linearly by a constant discharge current; 2) a comparator for comparing the storage capacitor voltage to an upper threshold voltage and a lower threshold voltage. The comparator output drops to a negative saturation voltage (nullV(SAT)) when the storage capacitor voltage rises above the upper threshold voltage and rises to a positive saturation voltage (nullV(SAT)) when the storage capacitor voltage drops below the lower threshold voltage. The VCO also comprises: 3) a constant charge current source for injecting the constant charge current into the storage capacitor when the comparator output rises to the positive saturation voltage; and 4) a constant discharge current source for draining the constant discharge current from the storage capacitor when the comparator output drops to the negative saturation voltage.

Abstract translation: 公开了一种压控振荡器（VCO），其接收+ V（IN）和-V（IN）控制电压，并且输出具有由+ V（IN）和-V（IN）控制确定的振荡频率的VCO输出信号 电压。 该VCO包括：1）通过恒定充电电流线性地充电并通过恒定放电电流线性放电的存储电容器; 2）用于将存储电容器电压与上阈值电压和较低阈值电压进行比较的比较器。 当存储电容器电压下降到低于下限值时，当存储电容器电压上升到高于阈值电压并上升到正饱和电压（+ V（SAT））时，比较器输出下降到负饱和电压（-V（SAT）） 阈值电压。 VCO还包括：3）恒定的充电电流源，用于当比较器输出上升到正饱和电压时，将恒定的充电电流注入到存储电容器中; 以及4）恒定放电电流源，用于当比较器输出下降到负饱和电压时从存储电容器排出恒定的放电电流。

公开(公告)号：US20040103263A1

公开(公告)日：2004-05-27

申请号：US10301372

申请日：2002-11-21

Applicant: STMICROELECTRONICS, INC.

Inventor： Osvaldo Colavin ,  Davide Rizzo

IPC: G06F015/00

CPC classification number: G06F9/3885 ,  G06F9/3012 ,  G06F9/3824 ,  G06F9/3828 ,  G06F9/3853 ,  G06F9/3879 ,  G06F9/3891 ,  G06F15/8007 ,  G06F15/8015

Abstract: Clustered VLIW processing elements, each preferably simple and identical, are coupled by a runtime reconfigurable inter-cluster interconnect to form a coprocessor executing only those portions of a program having high instruction level parallelism. The initial portion of each program segment executed by the coprocessor reconfigures the interconnect, if necessary, or is skipped. Clusters may be directly connected to a subset of neighboring clusters, or indirectly connected to any other cluster, a hierarchy exposed to the programming model and enabling a larger number of clusters to be employed. The coprocessor is idled during remaining portions of the program to reduce power dissipation.

Abstract translation: 集群的VLIW处理元件，每个优选地是简单的和相同的，通过运行时可重配置的群间互连来耦合，以形成仅执行具有高指令级并行性的程序的那些部分的协处理器。 由协处理器执行的每个程序段的初始部分如果需要重新配置互连，或者被跳过。 集群可以直接连接到相邻集群的子集，或者间接地连接到任何其他集群，暴露于编程模型的层次结构，并且能够使用更多数量的集群。 协处理器在程序的剩余部分空闲，以减少功耗。

公开(公告)号：US20040101172A1

公开(公告)日：2004-05-27

申请号：US10335587

申请日：2002-12-31

Applicant: STMicroelectronics, Inc.

Inventor： Fred P. Lane

IPC: G06K009/00

CPC classification number: G06K9/00899 ,  G06K9/00013

Abstract: A finger imaging system for receiving the finger of a person being fingerprinted by an automated fingerprint reader. The system includes a finger imaging device having a finger receiving portion for receiving the finger to be fingerprinted. Extending outward from the finger receiving surface is a locator bar that is located to engage a crease of the subject finger when it is in approximately the desired position. The locator bar may be fixed by or movably attached to the finger receiving surface, or may protrude through the finger receiving surface, possibly being attached to an interior movement mechanism. The locator bar may clean the finger as it is being positioned, and may include sensors for sensing non-image information to verify the legitimacy of an offered finger. The locator bar may also include a shunt for diverting unwanted static electricity stored on the finger before it is positioned for fingerprinting.

Abstract translation: 一种手指成像系统，用于接收由自动指纹读取器指纹的人的手指。 该系统包括具有用于接收要被指纹的手指的手指接收部分的手指成像装置。 从手指接收表面向外延伸的是定位杆，当定位杆处于大致期望的位置时，定位杆可以接合主体手指的折痕。 定位杆可以由手指接收表面固定或移动地附接到手指接收表面，或者可以突出通过手指接收表面，可能附着到内部移动机构。 定位杆可以在手指定位时清洁手指，并且可以包括用于感测非图像信息以验证提供的手指的合法性的传感器。 定位杆还可以包括用于在存储在手指上用于指纹的位置之前转移存储在手指上的不需要的静电的分流器。