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公开(公告)号：US11637590B2
公开(公告)日：2023-04-25
申请号：US17364291
申请日：2021-06-30
Inventor： Sylvie Wuidart , Sophie Maurice
Abstract: A near-field communication device operates to transmit data by near-field communications techniques to another device. The near-field communication device includes a memory that stores a message to be transmitted in an ASCII format. The message is retrieved from the memory and transmitted using the near-field communications techniques in an ASCII format.
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公开(公告)号：US11614949B2
公开(公告)日：2023-03-28
申请号：US16899327
申请日：2020-06-11
Inventor： Loic Pallardy , Ignazio Antonino Urzi , Jean-Francis Duret
IPC: G06F13/40 , G06F9/4401 , G06F9/30 , G06F9/345 , G06F9/445
Abstract: An integrated circuit comprises a processing unit configured for booting up with a set of boot instructions, then for determining the size of the instructions of an application programme and potentially rebooting on its own initiative, while being reconfigured, in order for it to execute the instructions of the application program. Only one boot memory is needed as a consequence.
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公开(公告)号：US11567558B2
公开(公告)日：2023-01-31
申请号：US17111877
申请日：2020-12-04
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor： Gerald Briat
IPC: G06F1/3234 , G06F3/06 , G11C16/30
Abstract: A memory chip includes at least two memory blocks. In a method for controlling power supply for the memory blocks of the memory chip, each memory block receives a command for switching to standby mode. The commands are issued, for example by a processor, separately for each memory block in order to be able to individually place the memory block in standby mode.
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公开(公告)号：US20230015669A1
公开(公告)日：2023-01-19
申请号：US17945822
申请日：2022-09-15
Inventor： David AUCHERE , Claire LAPORTE , Deborah COGONI , Laurent SCHWARTZ
Abstract: An electronic device includes a carrier substrate with an electronic IC chip mounted on top of the carrier substrate. An encapsulation block on top of the front face of the carrier substrate embeds the IC chip. The encapsulation block has a through-void for positioning and confinement that extends through the encapsulation block to the top of the carrier substrate. At least one electronic component is positioned within the through-void and mounted to the top of the carrier substrate. Solder bumps or pads are located within the through-void to electrically connect the at least one electronic component to the carrier substrate.
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475.发明授权公开(公告)号：US11557566B2
公开(公告)日：2023-01-17
申请号：US16835793
申请日：2020-03-31
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor： David Auchere , Asma Hajji , Fabien Quercia , Jerome Lopez
IPC: H01L23/31 , H01L23/00 , H01L23/552
Abstract: An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire.
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Patent Agency Ranking
公开(公告)号：US11525851B2
公开(公告)日：2022-12-13
申请号：US16897777
申请日：2020-06-10
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor： Sebastien Cliquennois
IPC: G01R27/06 , G01R27/26 , H01L23/522
Abstract: A digital integrated circuit includes first areas of a substrate which incorporate digital functions and second areas of the substrate which are filler between first areas. A capacitance is provided by interdigitated metal-insulator-metal structures formed from a metallization level above the substrate. The structures of the capacitance are vertically aligned with one or more of the second areas.
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公开(公告)号：US20220391204A1
公开(公告)日：2022-12-08
申请号：US17829784
申请日：2022-06-01
Inventor： Pierre Gobin , Jeremy Ribeiro De Freitas
Abstract: A digital signal processor according to an embodiment comprises a processing stage. The processing stage is configured to receive Cartesian coordinates of a vector in a floating point format and to output polar coordinates of the vector in a floating point format. The processing stage comprises a first electronic circuit configured to iteratively implement, timed by a clock signal, a CORDIC algorithm in a floating point format.
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公开(公告)号：US20220382067A1
公开(公告)日：2022-12-01
申请号：US17661381
申请日：2022-04-29
Applicant: STMicroelectronics (Alps) SAS , STMicroelectronics (Grenoble 2) SAS , STMicroelectronics (Research & Development) Limited
Inventor： Quentin Mermillod-Anselme , Salim Bouchene , Adam Caley
Abstract: The present disclosure relates to an assembly for an electronic device comprising: a display screen; an optical light emitter adapted to emit an Infrared or near Infrared light beam through the display screen; the optical light emitter and the display screen being of the type that, when an unpolarized light beam from the optical light emitter passes through a region of the display screen, a white spot of a first intensity is formed in the region; a light polarizer positioned between the optical light emitter and the display screen, the light polarizer being orientated such that a white spot of a second intensity, lower than the first intensity, is formed when the light beam, from the optical light emitter and polarized by the light polarizer, passes through the region of the display screen.
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公开(公告)号：US20220376379A1
公开(公告)日：2022-11-24
申请号：US17742039
申请日：2022-05-11
Inventor： Romain COFFY , Georg KIMMICH
Abstract: A package includes an upper level mounted to a lower level. The upper level includes a stack formed by insulating layers and conductive elements and includes a first conductive track of an antenna. A plastic element rests on the stack. A first cavity is defined in the plastic element. A second conductive track of the antenna is located on a wall of the plastic element (for example, in or adjacent to the first cavity). A second cavity is also defined in the plastic element surrounding the first cavity. A third conductive track of the antenna is located on a wall of the plastic element (for example, in the second cavity). A third cavity is delimited between the upper and lower levels and an integrated circuit chip is mounted within the third cavity and electrically connected to the antenna.
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公开(公告)号：US20220374201A1
公开(公告)日：2022-11-24
申请号：US17747101
申请日：2022-05-18
Inventor： Pierre Gobin , Jeremy Ribeiro De Freitas
Abstract: A digital signal processor includes K first electronic circuits. The first inputs receive K groups of G successive coefficients of a polynomial. The polynomial are of degree N with N+1 coefficients, where K is a sub-multiple of N+1 greater than or equal to two and G is equal to (N+1)/K. The first electronic circuits are configured to simultaneously implement K respective Homer methods and deliver K output results. A second electronic circuit includes a first input configured to successively receive the output results of the first electronic circuits starting with the output result of the first electronic circuit having processed the highest rank coefficient of the coefficients. A second input is configured to receive a variable X and the second electronic circuit is configured to implement a Homer method and deliver a value of the polynomial for the variable X on the output of the second electronic circuit.
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