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公开(公告)号:US12249549B2
公开(公告)日:2025-03-11
申请号:US18630676
申请日:2024-04-09
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor: Jerome Lopez
Abstract: An encapsulation hood is fastened onto electrically conductive zones of a support substrate using springs. Each spring has a region in contact with an electrically conductive path contained in the encapsulation hood and another region in contact with a corresponding one of the electrically conductive zones. The fastening of the part of the encapsulation hood onto the support substrate compresses the springs and further utilizes a bead of insulating glue located between the compressed springs.
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公开(公告)号:US10292259B2
公开(公告)日:2019-05-14
申请号:US15142213
申请日:2016-04-29
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor: Laurent Marechal , Richard Rembert , Jerome Lopez
Abstract: An electronic device disclosed herein includes a first conductor layer, a first nonconducting layer, and a second conductor layer in a stacked arrangement. A signal carrying conductive via is formed in the first nonconducting layer and extends between the first conductor layer and the second conductor layer. A shielding conductive via is formed in the first nonconducting layer, is not electrically coupled to the signal carrying conductive via, and substantially completely surrounds the signal carrying conductive via in spaced apart relation thereto.
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公开(公告)号:US10224306B2
公开(公告)日:2019-03-05
申请号:US15602278
申请日:2017-05-23
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor: David Auchere , Asma Hajji , Fabien Quercia , Jerome Lopez
IPC: H01L23/552 , H01L23/00 , H01L23/31
Abstract: An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire.
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公开(公告)号:US20180122770A1
公开(公告)日:2018-05-03
申请号:US15602278
申请日:2017-05-23
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor: David Auchere , Asma Hajji , Fabien Quercia , Jerome Lopez
IPC: H01L23/00 , H01L23/552 , H01L23/31
CPC classification number: H01L24/85 , H01L23/3157 , H01L23/552 , H01L24/48 , H01L2224/48992 , H01L2224/48997 , H01L2224/8592
Abstract: An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire.
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公开(公告)号:US12218287B2
公开(公告)日:2025-02-04
申请号:US18503025
申请日:2023-11-06
Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS
Inventor: Olivier Zanellato , Remi Brechignac , Jerome Lopez
IPC: H01L33/48 , H01L31/0203 , H01L31/18 , H01L33/00
Abstract: The present description concerns a package for an electronic device. The package including a plate and a lateral wall, separated by a layer made of a bonding material and at least one region made of a material configured to form in the region an opening between the inside and the outside of the package when the package is heated.
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公开(公告)号:US11862757B2
公开(公告)日:2024-01-02
申请号:US17485010
申请日:2021-09-24
Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS
Inventor: Olivier Zanellato , Remi Brechignac , Jerome Lopez
IPC: H01L33/48 , H01L31/0203 , H01L31/18 , H01L33/00
CPC classification number: H01L33/483 , H01L31/0203 , H01L31/18 , H01L33/005
Abstract: The present description concerns a package for an electronic device. The package including a plate and a lateral wall, separated by a layer made of a bonding material and at least one region made of a material configured to form in the region an opening between the inside and the outside of the package when the package is heated.
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公开(公告)号:US20170318664A1
公开(公告)日:2017-11-02
申请号:US15142213
申请日:2016-04-29
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor: Laurent Marechal , Richard Rembert , Jerome Lopez
CPC classification number: H05K1/0251 , H05K1/0222
Abstract: An electronic device disclosed herein includes a first conductor layer, a first nonconducting layer, and a second conductor layer in a stacked arrangement. A signal carrying conductive via is formed in the first nonconducting layer and extends between the first conductor layer and the second conductor layer. A shielding conductive via is formed in the first nonconducting layer, is not electrically coupled to the signal carrying conductive via, and substantially completely surrounds the signal carrying conductive via in spaced apart relation thereto.
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公开(公告)号:US12170262B2
公开(公告)日:2024-12-17
申请号:US18081884
申请日:2022-12-15
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor: David Auchere , Asma Hajji , Fabien Quercia , Jerome Lopez
IPC: H01L23/00 , H01L23/31 , H01L23/552
Abstract: An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire.
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公开(公告)号:US11984373B2
公开(公告)日:2024-05-14
申请号:US17522327
申请日:2021-11-09
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor: Jerome Lopez
CPC classification number: H01L23/3114 , H01L23/10 , H01L23/12 , H01L33/52
Abstract: An encapsulation hood is fastened onto electrically conductive zones of a support substrate using springs. Each spring has a region in contact with an electrically conductive path contained in the encapsulation hood and another region in contact with a corresponding one of the electrically conductive zones. The fastening of the part of the encapsulation hood onto the support substrate compresses the springs and further utilizes a bead of insulating glue located between the compressed springs.
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公开(公告)号:US11557566B2
公开(公告)日:2023-01-17
申请号:US16835793
申请日:2020-03-31
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor: David Auchere , Asma Hajji , Fabien Quercia , Jerome Lopez
IPC: H01L23/31 , H01L23/00 , H01L23/552
Abstract: An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire.
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