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    Method and Apparatus for Packing Packed Data
    46.
    发明申请
    Method and Apparatus for Packing Packed Data 失效
    包装数据的方法和装置

    公开(公告)号：US20130117539A1

    公开(公告)日：2013-05-09

    申请号：US13730831

    申请日：2012-12-29

    Applicant: Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan

    Inventor： Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan

    IPC: G06F9/30

    CPC classification number: G06F9/30036 ,  G06F7/49921 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30192 ,  G06F9/30196

    Abstract: An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.

    Abstract translation: 一种装置包括指令解码器，第一和第二源寄存器以及耦合到解码器的电路，用于从源寄存器接收压缩数据，并根据解码器接收到的解包指令对打包数据进行解包。 从第一源寄存器接收第一打包数据元素和第三打包数据元素。 从第二源寄存器接收第二打包数据元素和第四打包数据元素。 所述电路将打包的数据元素复制到目的地寄存器中，其中与第一打包数据元素相邻的第二打包数据元素，与第二打包数据元素相邻的第三打包数据元素以及与第三打包数据元素相邻的第四打包数据元素 数据元素。

    Packing two packed signed data in registers with saturation
    48.
    发明授权
    Packing two packed signed data in registers with saturation 失效
    在饱和的寄存器中打包两个打包的签名数据

    公开(公告)号：US08190867B2

    公开(公告)日：2012-05-29

    申请号：US13108723

    申请日：2011-05-16

    Applicant: Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan

    Inventor： Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan

    IPC: G06F9/315

    CPC classification number: G06F9/30036 ,  G06F7/49921 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30192 ,  G06F9/30196

    Abstract: A processor comprising a register file, and a decoder to decode an instruction to specify a first source register having a first packed signed 16-bit integers, and to specify a second source register having a second packed signed 16-bit integers. A functional unit to generate a result to be stored in a specified destination. The result including a third packed 8-bit integers including an integer for each integer in the first packed integers, and an integer for each integer in the second packed integers. The integers corresponding to the first packed integers next to one another in the result. The integers corresponding to the second packed integers next to one another. A highest order integer of the result corresponding to a highest order integer of the first packed integers. A lowest order integer of the result corresponding to a lowest order integer of the second packed integers.

    Abstract translation: 一种处理器，包括寄存器文件和解码器，用于解码指定第一源寄存器的指令，该第一源寄存器具有第一打包符号的16位整数，并且指定具有第二打包符号的16位整数的第二源寄存器。 用于生成要存储在指定目的地中的结果的功能单元。 结果包括第三个打包的8位整数，包括第一个打包整数中的每个整数的整数，以及第二个打包整数中的每个整数的整数。 对应于结果中彼此相邻的第一个打包整数的整数。 对应于彼此相邻的第二个打包整数的整数。 结果的最高阶整数对应于第一个打包整数的最高阶整数。 结果的最低阶整数对应于第二个打包整数的最低阶整数。

    System and method for fusing instructions
    49.
    发明授权
    System and method for fusing instructions 有权
    用于定影指令的系统和方法

    公开(公告)号：US07458069B2

    公开(公告)日：2008-11-25

    申请号：US10752875

    申请日：2004-01-06

    Applicant: Ronny Ronen ,  Alexander Peleg ,  Nathaniel Hoffman

    Inventor： Ronny Ronen ,  Alexander Peleg ,  Nathaniel Hoffman

    IPC: G06F9/45

    CPC classification number: G06F9/3001 ,  G06F9/30123 ,  G06F9/3017 ,  G06F9/3853 ,  G06F9/3893

    Abstract: A system and method for producing a fused instruction is described. In one embodiment, a first instruction and a second instruction that are both simple instructions (e.g., perform only one operation) and are dependent are fused together to create the fused instruction. The fused instruction has an opcode that represents the operation performed by the first instruction and the operation performed by the second instruction. The fused instruction has three source operands and one destination operand. Two of the three source operands are the two source operands of the first instruction, and the third source operand is the source operand of the second instruction that is not the destination operand of the first instruction. The destination operand of the fused instruction is the destination operand of the second instruction. An execution unit that can execute a fused instruction in one clock cycle is also disclosed. In one embodiment, the execution unit has two arithmetic logic units (“ALUs”), each of the ALUs performs one of the two operations of the fused instruction. The result of the first ALU is input into the second ALU to produce the desired result.

    Abstract translation: 描述用于产生融合指令的系统和方法。 在一个实施例中，作为简单指令（例如，仅执行一个操作）并且是依赖的第一指令和第二指令被融合在一起以创建融合指令。 融合指令具有表示由第一指令执行的操作和由第二指令执行的操作的操作码。 融合指令有三个源操作数和一个目标操作数。 三个源操作数中的两个是第一个指令的两个源操作数，第三个源操作数是不是第一个指令的目标操作数的第二个指令的源操作数。 融合指令的目标操作数是第二条指令的目标操作数。 还公开了可以在一个时钟周期执行融合指令的执行单元。 在一个实施例中，执行单元具有两个算术逻辑单元（“ALU”），每个ALU执行融合指令的两个操作之一。 将第一ALU的结果输入到第二ALU中以产生期望的结果。

    Method and apparatus to support an expanded register set
    50.
    发明授权
    Method and apparatus to support an expanded register set 有权
    支持扩展寄存器集的方法和装置

    公开(公告)号：US07363476B2

    公开(公告)日：2008-04-22

    申请号：US10625240

    申请日：2003-07-22

    Applicant: Opher D. Kahn ,  Alexander Peleg ,  Bob Valentine

    Inventor： Opher D. Kahn ,  Alexander Peleg ,  Bob Valentine

    IPC: G06F9/30 ,  G06F12/06

    CPC classification number: G06F9/30134 ,  G06F9/30138 ,  G06F9/30185 ,  G06F9/34

    Abstract: According to an embodiment of the present invention, a microprocessor includes an expanded logical register set that can be accessed by instructions including legacy opcodes and remapped addressing mode information. The known IA-32 instruction set is limited to accessing eight logical general integer registers. An IA-32 instruction can specify which of the eight logical general integer registers are to be accessed via 3-bit register identifier fields of the addressing mode information of the instruction. Each 3-bit register identifier can specify any of the eight logical general integer registers. An expanded logical register set (e.g., sixteen logical registers, thirty-two logical registers, sixty-four logical registers, etc.) can be accessed by remapping the addressing mode information to include at least four-bit register identifiers without defining new opcodes or defining additional instruction prefixes.

    Abstract translation: 根据本发明的实施例，微处理器包括扩展的逻辑寄存器组，其可由包括传统操作码和重新映射的寻址模式信息的指令访问。 已知的IA-32指令集仅限于访问8个逻辑通用整数寄存器。 IA-32指令可以通过指令的寻址模式信息的3位寄存器标识符字段来指定8个逻辑通用整数寄存器中的哪一个。 每个3位寄存器标识符可以指定八个逻辑通用整数寄存器中的任何一个。 扩展的逻辑寄存器组（例如，十六个逻辑寄存器，三十二个逻辑寄存器，六十四个逻辑寄存器等）可以通过重新映射寻址模式信息来包括至少四位寄存器标识符而不定义新的操作码或 定义附加指令前缀。

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