公开(公告)号：US07754555B2

公开(公告)日：2010-07-13

申请号：US11674713

申请日：2007-02-14

Applicant: Andreas Gehring ,  Ralf Van Bentum ,  Markus Lenski

Inventor： Andreas Gehring ,  Ralf Van Bentum ,  Markus Lenski

IPC: H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/823412 ,  H01L21/82345 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7845 ,  H01L29/7848

Abstract: By forming a stressed semiconductor material in a gate electrode, a biaxial tensile strain may be induced in the channel region, thereby significantly increasing the charge carrier mobility. This concept may be advantageously combined with additional strain-inducing sources, such as embedded strained semiconductor materials in the drain and source regions, thereby providing the potential for enhancing transistor performance without contributing to process complexity.

Abstract translation: 通过在栅电极中形成应力半导体材料，可以在沟道区域中诱发双轴拉伸应变，从而显着提高载流子迁移率。 该概念可以有利地与额外的应变诱发源（例如在漏极和源极区域中的嵌入式应变半导体材料）结合，从而提供增强晶体管性能的潜力，而不会造成工艺复杂性。

公开(公告)号：US07713763B2

公开(公告)日：2010-05-11

申请号：US12132014

申请日：2008-06-03

Applicant: Anthony Mowry ,  Casey Scott ,  Vassilios Papageorgiou ,  Andy Wei ,  Markus Lenski ,  Andreas Gehring

Inventor： Anthony Mowry ,  Casey Scott ,  Vassilios Papageorgiou ,  Andy Wei ,  Markus Lenski ,  Andreas Gehring

IPC: H01L21/00

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L22/34 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833

Abstract: By providing a test structure for evaluating the patterning process and/or the epitaxial growth process for forming embedded semiconductor alloys in sophisticated semiconductor devices, enhanced statistical relevance in combination with reduced test time may be accomplished.

Abstract translation: 通过提供用于评估用于在复杂半导体器件中形成嵌入式半导体合金的图案化工艺和/或外延生长工艺的测试结构，可以实现与减少的测试时间相结合的增强的统计相关性。

公开(公告)号：US20090294860A1

公开(公告)日：2009-12-03

申请号：US12394475

申请日：2009-02-27

Applicant: Anthony Mowry ,  Andy Wei ,  Andreas Gehring ,  Casey Scott

Inventor： Anthony Mowry ,  Andy Wei ,  Andreas Gehring ,  Casey Scott

IPC: H01L25/07 ,  H01L21/363 ,  H01L21/336

CPC classification number: H01L29/0847 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/41758 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/7848 ,  H01L29/78612 ,  H01L29/78621

Abstract: By repeatedly applying a process sequence comprising an etch process and a selective epitaxial growth process during the formation of drain and source areas in a transistor device, highly complex dopant profiles may be generated on the basis of in situ doping. Further-more, a strain material may be provided while stress relaxation mechanisms may be reduced due to the absence of any implantation processes.

Abstract translation: 通过在形成晶体管器件中的漏极和源极区域期间重复地应用包括蚀刻工艺和选择性外延生长工艺的工艺顺序，可以基于原位掺杂产生高度复杂的掺杂剂分布。 此外，可以提供应变材料，同时由于不存在任何植入过程而可以减小应力松弛机制。

公开(公告)号：US20080268585A1

公开(公告)日：2008-10-30

申请号：US11862296

申请日：2007-09-27

Applicant: Andreas Gehring ,  Jan Hoentschel ,  Andy Wei

Inventor： Andreas Gehring ,  Jan Hoentschel ,  Andy Wei

IPC: H01L21/84

CPC classification number: H01L21/8221 ,  H01L21/823481 ,  H01L21/823835 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/66128 ,  H01L29/8611

Abstract: A substrate diode for an SOI device is formed in accordance with an appropriately designed manufacturing flow, wherein transistor performance enhancing mechanisms may be implemented substantially without affecting the diode characteristics. In one aspect, respective openings for the substrate diode may be formed after the formation of a corresponding sidewall spacer structure used for defining the drain and source regions, thereby obtaining a significant lateral distribution of the dopants in the diode areas, which may therefore provide sufficient process margins during a subsequent silicidation sequence on the basis of a removal of the spacers in the transistor devices. In a further aspect, in addition to or alternatively, an offset spacer may be formed substantially without affecting the configuration of respective transistor devices.

Abstract translation: 根据适当设计的制造流程形成用于SOI器件的衬底二极管，其中可以基本上实现晶体管性能增强机制而不影响二极管特性。 在一个方面，用于衬底二极管的相应开口可以在形成用于限定漏极和源极区域的相应的侧壁间隔结构形成之后形成，从而获得掺杂剂在二极管区域中的显着的横向分布，这可能因此提供足够的 基于去除晶体管器件中的间隔物，在随后的硅化序列期间的工艺余量。 在另一方面，除了或者可选地，可以基本上形成偏移间隔物而不影响各个晶体管器件的配置。