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1.发明授权Test structure for monitoring process characteristics for forming embedded semiconductor alloys in drain/source regions 有权用于监测在漏极/源极区域中形成嵌入式半导体合金的工艺特性的测试结构公开(公告)号：US08227266B2
公开(公告)日：2012-07-24
申请号：US12716472
申请日：2010-03-03
申请人： Anthony Mowry , Casey Scott , Vassilios Papageorgiou , Andy Wei , Markus Lenski , Andreas Gehring
发明人： Anthony Mowry , Casey Scott , Vassilios Papageorgiou , Andy Wei , Markus Lenski , Andreas Gehring
IPC分类号： H01L21/00
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L22/34 , H01L29/165 , H01L29/6659 , H01L29/66636 , H01L29/7833
摘要： By providing a test structure for evaluating the patterning process and/or the epitaxial growth process for forming embedded semiconductor alloys in sophisticated semiconductor devices, enhanced statistical relevance in combination with reduced test time may be accomplished.
摘要翻译： 通过提供用于评估用于在复杂半导体器件中形成嵌入式半导体合金的图案化工艺和/或外延生长工艺的测试结构，可以实现与减少的测试时间相结合的增强的统计相关性。
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2.发明申请TEST STRUCTURE FOR MONITORING PROCESS CHARACTERISTICS FOR FORMING EMBEDDED SEMICONDUCTOR ALLOYS IN DRAIN/SOURCE REGIONS 有权用于在排水/源区域形成嵌入式半导体合金的监测过程特性的测试结构公开(公告)号：US20090166618A1
公开(公告)日：2009-07-02
申请号：US12132014
申请日：2008-06-03
申请人： Anthony Mowry , Casey Scott , Vassilios Papageorgiou , Andy Wei , Markus Lenski , Andreas Gehring
发明人： Anthony Mowry , Casey Scott , Vassilios Papageorgiou , Andy Wei , Markus Lenski , Andreas Gehring
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L22/34 , H01L29/165 , H01L29/6659 , H01L29/66636 , H01L29/7833
摘要： By providing a test structure for evaluating the patterning process and/or the epitaxial growth process for forming embedded semiconductor alloys in sophisticated semiconductor devices, enhanced statistical relevance in combination with reduced test time may be accomplished.
摘要翻译： 通过提供用于评估用于在复杂半导体器件中形成嵌入式半导体合金的图案化工艺和/或外延生长工艺的测试结构，可以实现与减少的测试时间相结合的增强的统计相关性。
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3.发明申请TEST STRUCTURE FOR MONITORING PROCESS CHARACTERISTICS FOR FORMING EMBEDDED SEMICONDUCTOR ALLOYS IN DRAIN/SOURCE REGIONS 有权用于在排水/源区域形成嵌入式半导体合金的监测过程特性的测试结构公开(公告)号：US20100155727A1
公开(公告)日：2010-06-24
申请号：US12716472
申请日：2010-03-03
申请人： ANTHONY MOWRY , Casey Scott , Vassilios Papageorgiou , Andy Wei , Markus Lenski , Andreas Gehring
发明人： ANTHONY MOWRY , Casey Scott , Vassilios Papageorgiou , Andy Wei , Markus Lenski , Andreas Gehring
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L22/34 , H01L29/165 , H01L29/6659 , H01L29/66636 , H01L29/7833
摘要： By providing a test structure for evaluating the patterning process and/or the epitaxial growth process for forming embedded semiconductor alloys in sophisticated semiconductor devices, enhanced statistical relevance in combination with reduced test time may be accomplished.
摘要翻译： 通过提供用于评估用于在复杂半导体器件中形成嵌入式半导体合金的图案化工艺和/或外延生长工艺的测试结构，可以实现与减少的测试时间相结合的增强的统计相关性。
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4.发明申请TEST STRUCTURE FOR MONITORING PROCESS CHARACTERISTICS FOR FORMING EMBEDDED SEMICONDUCTOR ALLOYS IN DRAIN/SOURCE REGIONS 有权用于在排水/源区域形成嵌入式半导体合金的监测过程特性的测试结构公开(公告)号：US20120223309A1
公开(公告)日：2012-09-06
申请号：US13474934
申请日：2012-05-18
申请人： Anthony Mowry , Casey Scott , Vassilios Papageorgiou , Andy Wei , Markus Lenski , Andreas Gehring
发明人： Anthony Mowry , Casey Scott , Vassilios Papageorgiou , Andy Wei , Markus Lenski , Andreas Gehring
IPC分类号： H01L23/58
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L22/34 , H01L29/165 , H01L29/6659 , H01L29/66636 , H01L29/7833
摘要： By providing a test structure for evaluating the patterning process and/or the epitaxial growth process for forming embedded semiconductor alloys in sophisticated semiconductor devices, enhanced statistical relevance in combination with reduced test time may be accomplished.
摘要翻译： 通过提供用于评估用于在复杂半导体器件中形成嵌入式半导体合金的图案化工艺和/或外延生长工艺的测试结构，可以实现与减少的测试时间相结合的增强的统计相关性。
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5.发明授权Test structure for monitoring process characteristics for forming embedded semiconductor alloys in drain/source regions 有权用于监测在漏极/源极区域中形成嵌入式半导体合金的工艺特性的测试结构公开(公告)号：US08530894B2
公开(公告)日：2013-09-10
申请号：US13474934
申请日：2012-05-18
申请人： Anthony Mowry , Casey Scott , Vassilios Papageorgiou , Andy Wei , Markus Lenski , Andreas Gehring
发明人： Anthony Mowry , Casey Scott , Vassilios Papageorgiou , Andy Wei , Markus Lenski , Andreas Gehring
IPC分类号： H01L21/00
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L22/34 , H01L29/165 , H01L29/6659 , H01L29/66636 , H01L29/7833
摘要： By providing a test structure for evaluating the patterning process and/or the epitaxial growth process for forming embedded semiconductor alloys in sophisticated semiconductor devices, enhanced statistical relevance in combination with reduced test time may be accomplished.
摘要翻译： 通过提供用于评估用于在复杂半导体器件中形成嵌入式半导体合金的图案化工艺和/或外延生长工艺的测试结构，可以实现与减少的测试时间相结合的增强的统计相关性。
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6.发明授权Test structure for monitoring process characteristics for forming embedded semiconductor alloys in drain/source regions 有权用于监测在漏极/源极区域中形成嵌入式半导体合金的工艺特性的测试结构公开(公告)号：US07713763B2
公开(公告)日：2010-05-11
申请号：US12132014
申请日：2008-06-03
申请人： Anthony Mowry , Casey Scott , Vassilios Papageorgiou , Andy Wei , Markus Lenski , Andreas Gehring
发明人： Anthony Mowry , Casey Scott , Vassilios Papageorgiou , Andy Wei , Markus Lenski , Andreas Gehring
IPC分类号： H01L21/00
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L22/34 , H01L29/165 , H01L29/6659 , H01L29/66636 , H01L29/7833
摘要： By providing a test structure for evaluating the patterning process and/or the epitaxial growth process for forming embedded semiconductor alloys in sophisticated semiconductor devices, enhanced statistical relevance in combination with reduced test time may be accomplished.
摘要翻译： 通过提供用于评估用于在复杂半导体器件中形成嵌入式半导体合金的图案化工艺和/或外延生长工艺的测试结构，可以实现与减少的测试时间相结合的增强的统计相关性。
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7.发明申请STRAIN ENHANCEMENT IN TRANSISTORS COMPRISING AN EMBEDDED STRAIN-INDUCING SEMICONDUCTOR ALLOY BY CREATING A PATTERNING NON-UNIFORMITY AT THE BOTTOM OF THE GATE ELECTRODE 有权通过在门电极底部形成图案非均匀性来包含嵌入式应变诱导半导体合金的晶体管中的应变增强公开(公告)号：US20100301421A1
公开(公告)日：2010-12-02
申请号：US12772436
申请日：2010-05-03
IPC分类号： H01L27/092 , H01L21/336 , H01L21/8238
CPC分类号： H01L29/7848 , H01L21/28088 , H01L21/28114 , H01L21/28247 , H01L21/823418 , H01L21/823807 , H01L21/823814 , H01L21/82385 , H01L21/823864 , H01L27/092 , H01L29/42376 , H01L29/4966 , H01L29/51
摘要： Performance of P-channel transistors may be enhanced on the basis of an embedded strain-inducing semiconductor alloy by forming a gate electrode structure on the basis of a high-k dielectric material in combination with a metal-containing cap layer in order to obtain an undercut configuration of the gate electrode structure. Consequently, the strain-inducing semiconductor alloy may be formed on the basis of a sidewall spacer of minimum thickness in order to position the strain-inducing semiconductor material closer to a central area of the channel region.
摘要翻译： 基于嵌入式应变诱发半导体合金，可以通过基于高k介电材料与含金属盖层组合形成栅电极结构来增强P沟道晶体管的性能，以获得 栅电极结构的底切配置。 因此，应变诱导半导体合金可以基于最小厚度的侧壁间隔物形成，以便使应变诱导半导体材料更靠近沟道区的中心区域。
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8.发明授权Strain enhancement in transistors comprising an embedded strain-inducing semiconductor alloy by creating a patterning non-uniformity at the bottom of the gate electrode 有权通过在栅电极的底部产生图案化不均匀性，包括嵌入式应变诱导半导体合金的晶体管中的应变增强公开(公告)号：US08357573B2
公开(公告)日：2013-01-22
申请号：US12772436
申请日：2010-05-03
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L29/7848 , H01L21/28088 , H01L21/28114 , H01L21/28247 , H01L21/823418 , H01L21/823807 , H01L21/823814 , H01L21/82385 , H01L21/823864 , H01L27/092 , H01L29/42376 , H01L29/4966 , H01L29/51
摘要： Performance of P-channel transistors may be enhanced on the basis of an embedded strain-inducing semiconductor alloy by forming a gate electrode structure on the basis of a high-k dielectric material in combination with a metal-containing cap layer in order to obtain an undercut configuration of the gate electrode structure. Consequently, the strain-inducing semiconductor alloy may be formed on the basis of a sidewall spacer of minimum thickness in order to position the strain-inducing semiconductor material closer to a central area of the channel region.
摘要翻译： 基于嵌入式应变诱发半导体合金，可以通过基于高k介电材料与含金属盖层组合形成栅电极结构来增强P沟道晶体管的性能，以获得 栅电极结构的底切配置。 因此，应变诱导半导体合金可以基于最小厚度的侧壁间隔物形成，以便使应变诱导半导体材料更靠近沟道区的中心区域。
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9.发明申请GRADED WELL IMPLANTATION FOR ASYMMETRIC TRANSISTORS HAVING REDUCED GATE ELECTRODE PITCHES 有权具有减少栅极电极板的不对称晶体管的分级井植入公开(公告)号：US20100193866A1
公开(公告)日：2010-08-05
申请号：US12692886
申请日：2010-01-25
IPC分类号： H01L27/088 , H01L21/77
CPC分类号： H01L21/266 , H01L21/2652 , H01L21/26586 , H01L21/823493 , H01L29/6659 , H01L29/7833
摘要： In sophisticated semiconductor devices, an asymmetric transistor configuration may be obtained on the basis of an asymmetric well implantation while avoiding a tilted implantation process. For this purpose, a graded implantation mask may be formed, such as a graded resist mask, which may have a higher ion blocking capability at the drain side compared to the source side of the asymmetric transistor. For instance, the asymmetric configuration may be obtained on the basis of a non-tilted implantation process with a high degree of performance gain and may be accomplished irrespective of the technology standard under consideration.
摘要翻译： 在复杂的半导体器件中，可以在不对称阱注入的基础上获得不对称晶体管配置，同时避免倾斜的注入工艺。 为此，可以形成渐变注入掩模，例如渐变抗蚀剂掩模，其在不对称晶体管的源极侧可能在漏极侧具有更高的离子阻挡能力。 例如，可以在具有高度性能增益的非倾斜注入工艺的基础上获得不对称构造，并且可以不考虑所考虑的技术标准而实现。
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10.发明授权Graded well implantation for asymmetric transistors having reduced gate electrode pitches 有权对具有减小的栅电极间距的不对称晶体管进行分级阱注入公开(公告)号：US09449826B2
公开(公告)日：2016-09-20
申请号：US12692886
申请日：2010-01-25
IPC分类号： H01L21/8234 , H01L21/336 , H01L21/266 , H01L21/265 , H01L29/66 , H01L29/78
CPC分类号： H01L21/266 , H01L21/2652 , H01L21/26586 , H01L21/823493 , H01L29/6659 , H01L29/7833
摘要： In sophisticated semiconductor devices, an asymmetric transistor configuration may be obtained on the basis of an asymmetric well implantation while avoiding a tilted implantation process. For this purpose, a graded implantation mask may be formed, such as a graded resist mask, which may have a higher ion blocking capability at the drain side compared to the source side of the asymmetric transistor. For instance, the asymmetric configuration may be obtained on the basis of a non-tilted implantation process with a high degree of performance gain and may be accomplished irrespective of the technology standard under consideration.
摘要翻译： 在复杂的半导体器件中，可以在不对称阱注入的基础上获得不对称晶体管配置，同时避免倾斜的注入工艺。 为此，可以形成渐变注入掩模，例如渐变抗蚀剂掩模，其在不对称晶体管的源极侧可能在漏极侧具有更高的离子阻挡能力。 例如，可以在具有高度性能增益的非倾斜注入工艺的基础上获得不对称构造，并且可以不考虑所考虑的技术标准而实现。
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