公开(公告)号：US08377761B2

公开(公告)日：2013-02-19

申请号：US13081575

申请日：2011-04-07

申请人： Andreas Gehring ,  Jan Hoentschel ,  Andy Wei

发明人： Andreas Gehring ,  Jan Hoentschel ,  Andy Wei

IPC分类号： H01L21/84

CPC分类号： H01L21/8221 ,  H01L21/823481 ,  H01L21/823835 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/66128 ,  H01L29/8611

摘要： A substrate diode for an SOI device is formed in accordance with an appropriately designed manufacturing flow, wherein transistor performance enhancing mechanisms may be implemented substantially without affecting the diode characteristics. In one aspect, respective openings for the substrate diode may be formed after the formation of a corresponding sidewall spacer structure used for defining the drain and source regions, thereby obtaining a significant lateral distribution of the dopants in the diode areas, which may therefore provide sufficient process margins during a subsequent silicidation sequence on the basis of a removal of the spacers in the transistor devices. In a further aspect, in addition to or alternatively, an offset spacer may be formed substantially without affecting the configuration of respective transistor devices.

摘要翻译： 根据适当设计的制造流程形成用于SOI器件的衬底二极管，其中可以基本上实现晶体管性能增强机制而不影响二极管特性。 在一个方面，用于衬底二极管的相应开口可以在形成用于限定漏极和源极区域的相应的侧壁间隔结构形成之后形成，从而获得掺杂剂在二极管区域中的显着的横向分布，这可能因此提供足够的 基于去除晶体管器件中的间隔物，在随后的硅化序列期间的工艺余量。 在另一方面，除了或者可选地，可以基本上形成偏移间隔物而不影响各个晶体管器件的配置。

公开(公告)号：US07943442B2

公开(公告)日：2011-05-17

申请号：US11862296

申请日：2007-09-27

申请人： Andreas Gehring ,  Jan Hoentschel ,  Andy Wei

发明人： Andreas Gehring ,  Jan Hoentschel ,  Andy Wei

IPC分类号： H01L21/84

CPC分类号： H01L21/8221 ,  H01L21/823481 ,  H01L21/823835 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/66128 ,  H01L29/8611

摘要： A substrate diode for an SOI device is formed in accordance with an appropriately designed manufacturing flow, wherein transistor performance enhancing mechanisms may be implemented substantially without affecting the diode characteristics. In one aspect, respective openings for the substrate diode may be formed after the formation of a corresponding sidewall spacer structure used for defining the drain and source regions, thereby obtaining a significant lateral distribution of the dopants in the diode areas, which may therefore provide sufficient process margins during a subsequent silicidation sequence on the basis of a removal of the spacers in the transistor devices. In a further aspect, in addition to or alternatively, an offset spacer may be formed substantially without affecting the configuration of respective transistor devices.

摘要翻译： 根据适当设计的制造流程形成用于SOI器件的衬底二极管，其中可以基本上实现晶体管性能增强机制而不影响二极管特性。 在一个方面，用于衬底二极管的相应开口可以在形成用于限定漏极和源极区域的相应的侧壁间隔结构形成之后形成，从而获得掺杂剂在二极管区域中的显着的横向分布，这可能因此提供足够的 基于去除晶体管器件中的间隔物，在随后的硅化序列期间的工艺余量。 在另一方面，除了或者可选地，可以基本上形成偏移间隔物而不影响各个晶体管器件的配置。

公开(公告)号：US20110183477A1

公开(公告)日：2011-07-28

申请号：US13081575

申请日：2011-04-07

申请人： Andreas Gehring ,  Jan Hoentschel ,  Andy Wei

发明人： Andreas Gehring ,  Jan Hoentschel ,  Andy Wei

IPC分类号： H01L21/84

CPC分类号： H01L21/8221 ,  H01L21/823481 ,  H01L21/823835 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/66128 ,  H01L29/8611

摘要： A substrate diode for an SOI device is formed in accordance with an appropriately designed manufacturing flow, wherein transistor performance enhancing mechanisms may be implemented substantially without affecting the diode characteristics. In one aspect, respective openings for the substrate diode may be formed after the formation of a corresponding sidewall spacer structure used for defining the drain and source regions, thereby obtaining a significant lateral distribution of the dopants in the diode areas, which may therefore provide sufficient process margins during a subsequent silicidation sequence on the basis of a removal of the spacers in the transistor devices. In a further aspect, in addition to or alternatively, an offset spacer may be formed substantially without affecting the configuration of respective transistor devices.

摘要翻译： 根据适当设计的制造流程形成用于SOI器件的衬底二极管，其中可以基本上实现晶体管性能增强机制而不影响二极管特性。 在一个方面，用于衬底二极管的相应开口可以在形成用于限定漏极和源极区域的相应的侧壁间隔结构形成之后形成，从而获得掺杂剂在二极管区域中的显着的横向分布，这可能因此提供足够的 基于去除晶体管器件中的间隔物，在随后的硅化序列期间的工艺余量。 在另一方面，除了或者可选地，可以基本上形成偏移间隔物而不影响各个晶体管器件的配置。

公开(公告)号：US20080268585A1

公开(公告)日：2008-10-30

申请号：US11862296

申请日：2007-09-27

申请人： Andreas Gehring ,  Jan Hoentschel ,  Andy Wei

发明人： Andreas Gehring ,  Jan Hoentschel ,  Andy Wei

IPC分类号： H01L21/84

CPC分类号： H01L21/8221 ,  H01L21/823481 ,  H01L21/823835 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/66128 ,  H01L29/8611

摘要： A substrate diode for an SOI device is formed in accordance with an appropriately designed manufacturing flow, wherein transistor performance enhancing mechanisms may be implemented substantially without affecting the diode characteristics. In one aspect, respective openings for the substrate diode may be formed after the formation of a corresponding sidewall spacer structure used for defining the drain and source regions, thereby obtaining a significant lateral distribution of the dopants in the diode areas, which may therefore provide sufficient process margins during a subsequent silicidation sequence on the basis of a removal of the spacers in the transistor devices. In a further aspect, in addition to or alternatively, an offset spacer may be formed substantially without affecting the configuration of respective transistor devices.

摘要翻译： 根据适当设计的制造流程形成用于SOI器件的衬底二极管，其中可以基本上实现晶体管性能增强机制而不影响二极管特性。 在一个方面，用于衬底二极管的相应开口可以在形成用于限定漏极和源极区域的相应的侧壁间隔结构形成之后形成，从而获得掺杂剂在二极管区域中的显着的横向分布，这可能因此提供足够的 基于去除晶体管器件中的间隔物，在随后的硅化序列期间的工艺余量。 在另一方面，除了或者可选地，可以基本上形成偏移间隔物而不影响各个晶体管器件的配置。

公开(公告)号：US20080081403A1

公开(公告)日：2008-04-03

申请号：US11740072

申请日：2007-04-25

申请人： Andreas Gehring ,  Markus Lenski ,  Jan Hoentschel ,  Thorsten Kammler

发明人： Andreas Gehring ,  Markus Lenski ,  Jan Hoentschel ,  Thorsten Kammler

IPC分类号： H01L21/337

CPC分类号： H01L29/045 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/268 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7843

摘要： By appropriately adapting the length direction and width directions of transistor devices with respect to the crystallographic orientation of the semiconductor material such that identical vertical and horizontal growth planes upon re-crystallizing amorphized portions are obtained, the number of corresponding stacking faults may be significantly reduced. Hence, transistor elements with extremely shallow PN junctions may be formed on the basis of pre-amorphization implantation processes while substantially avoiding any undue side effects typically obtained in conventional techniques due to stacking faults.

摘要翻译： 通过适当地适应晶体管器件的长度方向和宽度方向相对于半导体材料的晶体取向，使得在重新结晶非晶化部分时相同的垂直和水平生长面，可以显着地减少对应的堆垛层错的数量。 因此，具有非常浅的PN结的晶体管元件可以基于前非晶化注入工艺形成，同时基本上避免了由于堆垛层错而在常规技术中通常获得的任何不适当的副作用。

公开(公告)号：US07763505B2

公开(公告)日：2010-07-27

申请号：US11740072

申请日：2007-04-25

申请人： Andreas Gehring ,  Markus Lenski ,  Jan Hoentschel ,  Thorsten Kammler

发明人： Andreas Gehring ,  Markus Lenski ,  Jan Hoentschel ,  Thorsten Kammler

IPC分类号： H01L21/337

CPC分类号： H01L29/045 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/268 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7843

摘要： By appropriately adapting the length direction and width directions of transistor devices with respect to the crystallographic orientation of the semiconductor material such that identical vertical and horizontal growth planes upon re-crystallizing amorphized portions are obtained, the number of corresponding stacking faults may be significantly reduced. Hence, transistor elements with extremely shallow PN junctions may be formed on the basis of pre-amorphization implantation processes while substantially avoiding any undue side effects typically obtained in conventional techniques due to stacking faults.

摘要翻译： 通过适当地适应晶体管器件的长度方向和宽度方向相对于半导体材料的晶体取向，使得在重新结晶非晶化部分时相同的垂直和水平生长面，可以显着地减少对应的堆垛层错的数量。 因此，具有非常浅的PN结的晶体管元件可以基于前非晶化注入工艺形成，同时基本上避免了由于堆垛层错而在常规技术中通常获得的任何不适当的副作用。

公开(公告)号：US09449826B2

公开(公告)日：2016-09-20

申请号：US12692886

申请日：2010-01-25

申请人： G Robert Mulfinger ,  Andy Wei ,  Jan Hoentschel ,  Vassilios Papageorgiou

发明人： G Robert Mulfinger ,  Andy Wei ,  Jan Hoentschel ,  Vassilios Papageorgiou

IPC分类号： H01L21/8234 ,  H01L21/336 ,  H01L21/266 ,  H01L21/265 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/266 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/823493 ,  H01L29/6659 ,  H01L29/7833

摘要： In sophisticated semiconductor devices, an asymmetric transistor configuration may be obtained on the basis of an asymmetric well implantation while avoiding a tilted implantation process. For this purpose, a graded implantation mask may be formed, such as a graded resist mask, which may have a higher ion blocking capability at the drain side compared to the source side of the asymmetric transistor. For instance, the asymmetric configuration may be obtained on the basis of a non-tilted implantation process with a high degree of performance gain and may be accomplished irrespective of the technology standard under consideration.

摘要翻译： 在复杂的半导体器件中，可以在不对称阱注入的基础上获得不对称晶体管配置，同时避免倾斜的注入工艺。 为此，可以形成渐变注入掩模，例如渐变抗蚀剂掩模，其在不对称晶体管的源极侧可能在漏极侧具有更高的离子阻挡能力。 例如，可以在具有高度性能增益的非倾斜注入工艺的基础上获得不对称构造，并且可以不考虑所考虑的技术标准而实现。

公开(公告)号：US08404550B2

公开(公告)日：2013-03-26

申请号：US12905383

申请日：2010-10-15

申请人： Thilo Scheiper ,  Sven Beyer ,  Andy Wei ,  Jan Hoentschel

发明人： Thilo Scheiper ,  Sven Beyer ,  Andy Wei ,  Jan Hoentschel

IPC分类号： H01L21/336

CPC分类号： H01L29/7848 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66651

摘要： In a P-channel transistor comprising a high-k metal gate electrode structure, a superior dopant profile may be obtained, at least in the threshold adjusting semiconductor material, such as a silicon/germanium material, by incorporating a diffusion blocking species, such as fluorine, prior to forming the threshold adjusting semiconductor material. Consequently, the drain and source extension regions may be provided with a high dopant concentration as required for obtaining the target Miller capacitance without inducing undue dopant diffusion below the threshold adjusting semiconductor material, which may otherwise result in increased leakage currents and increased risk of punch through events.

摘要翻译： 在包含高k金属栅电极结构的P沟道晶体管中，至少在阈值调节半导体材料（例如硅/锗材料）中可以通过掺入扩散阻挡物质获得优异的掺杂剂分布，例如 在形成阈值调节半导体材料之前。 因此，漏极和源极延伸区域可以被提供有高的掺杂剂浓度，以获得目标米勒电容，而不会导致低于阈值调节半导体材料的不适当的掺杂剂扩散，否则可能导致增加的漏电流和增加的穿孔风险 事件

公开(公告)号：US08183101B2

公开(公告)日：2012-05-22

申请号：US12620265

申请日：2009-11-17

申请人： Robert Mulfinger ,  Andy Wei ,  Jan Hoentschel ,  Andrew Waite

发明人： Robert Mulfinger ,  Andy Wei ,  Jan Hoentschel ,  Andrew Waite

IPC分类号： H01L29/78

CPC分类号： H01L29/66795 ,  H01L29/785

摘要： The drain and source regions of a multiple gate transistor may be formed without an epitaxial growth process by using a placeholder structure for forming the drain and source dopant profiles and subsequently masking the drain and source areas and removing the placeholder structures so as to expose the channel area of the transistor. Thereafter, corresponding fins may be patterned and a gate electrode structure may be formed. Consequently, reduced cycle times may be accomplished due to the avoidance of the epitaxial growth process.

摘要翻译： 多栅极晶体管的漏极和源极区可以通过使用用于形成漏极和源极掺杂物分布的占位符结构而形成，而不需要外延生长工艺，随后掩蔽漏极和源极区域并去除占位符结构以露出​​沟道 晶体管的面积。 此后，可以对相应的翅片进行构图，并且可以形成栅电极结构。 因此，由于避免了外延生长过程，可以实现缩短的循环时间。

公开(公告)号：US20110266633A1

公开(公告)日：2011-11-03

申请号：US12963364

申请日：2010-12-08

申请人： Sven Beyer ,  Klaus Hempel ,  Roland Stejskal ,  Andy Wei ,  Thilo Scheiper ,  Andreas Kurz ,  Uwe Griebenow ,  Jan Hoentschel

发明人： Sven Beyer ,  Klaus Hempel ,  Roland Stejskal ,  Andy Wei ,  Thilo Scheiper ,  Andreas Kurz ,  Uwe Griebenow ,  Jan Hoentschel

IPC分类号： H01L27/06 ,  H01L21/02

CPC分类号： H01L23/5252 ,  H01L23/5256 ,  H01L27/0629 ,  H01L29/66545 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a replacement gate approach, the semiconductor material or at least a significant portion thereof in a non-transistor structure, such as a precision resistor, an electronic fuse and the like, may be preserved upon replacing the semiconductor material in the gate electrode structures. To this end, an appropriate dielectric material may be provided at least prior to the removal of the semiconductor material in the gate electrode structures, without requiring significant modifications of established replacement gate approaches.

摘要翻译： 在替代栅极方法中，可以在更换栅电极结构中的半导体材料时保留半导体材料或其非晶体管结构中的至少其重要部分，例如精密电阻器，电子熔丝等。 为此，可以至少在去除栅电极结构中的半导体材料之前提供适当的介电材料，而不需要对建立的替代栅极方法进行显着的修改。