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    Method for creating tensile strain by repeatedly applied stress memorization techniques
    2.
    发明授权
    Method for creating tensile strain by repeatedly applied stress memorization techniques 有权
    通过重复应力记忆技术产生拉伸应变的方法

    公开(公告)号：US07790537B2

    公开(公告)日：2010-09-07

    申请号：US11937677

    申请日：2007-11-09

    Applicant: Andy Wei ,  Anthony Mowry ,  Andreas Gehring ,  Maciej Wiatr

    Inventor： Andy Wei ,  Anthony Mowry ,  Andreas Gehring ,  Maciej Wiatr

    IPC: H01L21/336

    CPC classification number: H01L29/7842 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/6656 ,  H01L29/7843

    Abstract: By introducing additional strain-inducing mechanisms on the basis of stress memorization techniques, the performance of NMOS transistors may be significantly increased, thereby reducing the imbalance between PMOS transistors and NMOS transistors. By amorphizing and re-crystallizing the respective material in the presence of a mask layer at various stages of the manufacturing process, a drive current improvement of up to approximately 27% has been observed, with the potential for further performance gain.

    Abstract translation: 通过在应力记忆技术的基础上引入额外的应变诱导机制，可以显着增加NMOS晶体管的性能，从而减少PMOS晶体管和NMOS晶体管之间的不平衡。 通过在制造过程的不同阶段在掩模层的存在下使各种材料非晶化并再结晶，已经观察到高达约27％的驱动电流改善，具有进一步性能增益的潜力。

    METHOD OF FORMING A SEMICONDUCTOR STRUCTURE COMPRISING A FIELD EFFECT TRANSISTOR HAVING A STRESSED CHANNEL REGION
    4.
    发明申请
    METHOD OF FORMING A SEMICONDUCTOR STRUCTURE COMPRISING A FIELD EFFECT TRANSISTOR HAVING A STRESSED CHANNEL REGION 有权
    形成具有应力通道区域的场效应晶体管的半导体结构的方法

    公开(公告)号：US20080102590A1

    公开(公告)日：2008-05-01

    申请号：US11750816

    申请日：2007-05-18

    Applicant: Andreas Gehring ,  Andy Wei ,  Anthony Mowry ,  Manuj Rathor

    Inventor： Andreas Gehring ,  Andy Wei ,  Anthony Mowry ,  Manuj Rathor

    IPC: H01L21/336 ,  H01L21/428

    CPC classification number: H01L29/7833 ,  H01L21/268 ,  H01L21/823807 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7843

    Abstract: A method of forming a semiconductor structure comprises providing a semiconductor substrate comprising a first transistor element and a second transistor element. The first transistor element comprises at least one first amorphous region and the second transistor element comprises at least one second amorphous region. A stress-creating layer is formed over the first transistor element. The stress-creating layer does not cover the second transistor element. A first annealing process is performed. The first annealing process is adapted to re-crystallize the first amorphous region and the second amorphous region. After the first annealing process, a second annealing process is performed. The stress-creating layer remains on the semiconductor substrate during the second annealing process.

    Abstract translation: 形成半导体结构的方法包括提供包括第一晶体管元件和第二晶体管元件的半导体衬底。 第一晶体管元件包括至少一个第一非晶区，而第二晶体管元件包括至少一个第二非晶区。 应力产生层形成在第一晶体管元件上。 应力产生层不覆盖第二晶体管元件。 执行第一退火处理。 第一退火工艺适于重新结晶第一非晶区域和第二非晶区域。 在第一退火处理之后，进行第二退火处理。 应力产生层在第二退火工艺期间保留在半导体衬底上。

    Method of encrypting or decrypting data packets of a data stream as well as a signal sequence and data processing system for performing the method
    5.
    发明申请
    Method of encrypting or decrypting data packets of a data stream as well as a signal sequence and data processing system for performing the method 审中-公开
    对数据流的数据包进行加密或解密的方法以及用于执行该方法的信号序列和数据处理系统

    公开(公告)号：US20080034197A1

    公开(公告)日：2008-02-07

    申请号：US11583108

    申请日：2006-10-19

    Applicant: Christian Engel ,  Thomas Berndes ,  Andreas Gehring

    Inventor： Christian Engel ,  Thomas Berndes ,  Andreas Gehring

    IPC: H04L9/00

    CPC classification number: H04L63/0428 ,  H04L63/06

    Abstract: This invention relates to a method of encrypting data packets of a data stream and decrypting plurally encrypted data of a data stream that provides an increased level of data security and can be automated using a signal sequence (a computer program product) or a data processing device. A data packet to be encrypted or a data packet to be decrypted is automatically encrypted or decrypted sequentially in at least two subsequent processing steps using different coding algorithms and different assigned coding keys. For encryption, a number, type, and sequence of different coding algorithms is first determined (S10) that is to be used in the subsequent encryption operations and respective different coding keys are assigned to the coding algorithms (S12, S13). Then the data packet to be encrypted is encrypted sequentially in at least two subsequent encryption operations (S16, S17) to obtain a plurally encrypted data packet. For decryption, an unencrypted coding characteristic assigned to the plurally encrypted data packet and specifying at least one coding algorithm and an assigned coding key is detected automatically. The coding characteristic thus allows sequential decryption in at least two subsequent decryption operations.

    Abstract translation: 本发明涉及一种对数据流的数据分组进行加密和解密数据流的多个加密数据的方法，该数据流提供了更高级别的数据安全性，并且可以使用信号序列（计算机程序产品）或数据处理设备 。 要加密的数据包或要解密的数据包在使用不同的编码算法和不同的分配的编码密钥的至少两个后续处理步骤中被顺序自动加密或解密。 对于加密，首先确定要在随后的加密操作中使用的不同编码算法的数量，类型和序列（S10），并将各个不同的编码密钥分配给编码算法（S12，S13）。 然后在至少两个后续加密操作中顺序地加密要加密的数据分组（S16，S17），以获得多个加密的数据分组。 对于解密，自动检测分配给多个加密数据包并指定至少一个编码算法和分配的编码密钥的未加密编码特性。 因此，编码特性允许在至少两个随后的解密操作中进行顺序解密。

    Network component for a communication network, communication network, and method of providing a data connection
    6.
    发明申请
    Network component for a communication network, communication network, and method of providing a data connection 审中-公开
    用于通信网络的网络组件，通信网络和提供数据连接的方法

    公开(公告)号：US20070076882A1

    公开(公告)日：2007-04-05

    申请号：US11522930

    申请日：2006-09-19

    Applicant: Christian Engel ,  Thomas Berndes ,  Andreas Gehring

    Inventor： Christian Engel ,  Thomas Berndes ,  Andreas Gehring

    IPC: H04K1/00

    CPC classification number: H04L63/0457

    Abstract: This invention relates to a network component (11-16) for a communication network (1) in which multiple communication interfaces (31-37) are connected for mutual data exchange via a transmission network (20) and in which said network component (11-16) can be placed between at least one assigned communication interface (31-37) and the transmission network (20). The network component (11-16) according to the invention comprises a first memory facility (41) for storing at least one preset coding key (K1, K2, K3), a decrypter (51) for decrypting the encrypted data received via the transmission network (20) using the stored at least one coding key (K1, K2, K3) as well as a data selector (52) for the selective transfer of data between the transmission network (20) and the at least one assigned communication interface (31-37). Said data selector (52) is designed to automatically prevent transfer of encrypted data received via the transmission network (20) to the at least one assigned communication interface (31-37) if the decrypter (51) cannot decrypt the encrypted data using the at least one coding key (K1, K2, K3). The invention further relates to a respective communication network and a respective method of providing a data connection among at least two communication interfaces that can be connected via a transmission network.

    Abstract translation: 本发明涉及一种用于通信网络（1）的网络组件（11-16），其中多个通信接口（31-37）经由传输网络（20）连接用于相互数据交换，并且其中所述网络组件 16）可以放置在至少一个分配的通信接口（31-37）和传输网络（20）之间。 根据本发明的网络组件（11-16）包括用于存储至少一个预设编码密钥（K 1，K 2，K 3）的第一存储设备（41），用于解密所接收的加密数据的解密器（51） 通过所述传输网络（20）使用所存储的至少一个编码密钥（K 1，K 2，K 3）以及数据选择器（52），用于在所述传输网络（20）和所述传输网络 至少一个分配的通信接口（31-37）。 所述数据选择器（52）被设计成如果所述解密器（51）不能使用所述至少一个分配的通信接口（31-37）解密所述加密数据，则自动防止经由所述传输网络（20）接收的加密数据传送到所述至少一个分配的通信接口（31-37） 至少一个编码密钥（K 1，K 2，K 3）。 本发明还涉及相应的通信网络以及在可以经由传输网络连接的至少两个通信接口之间提供数据连接的相应方法。

    SOI device having a substrate diode with process tolerant configuration and method of forming the SOI device
    8.
    发明授权
    SOI device having a substrate diode with process tolerant configuration and method of forming the SOI device 有权
    SOI器件具有具有工艺容限配置的衬底二极管和形成SOI器件的方法

    公开(公告)号：US07943442B2

    公开(公告)日：2011-05-17

    申请号：US11862296

    申请日：2007-09-27

    Applicant: Andreas Gehring ,  Jan Hoentschel ,  Andy Wei

    Inventor： Andreas Gehring ,  Jan Hoentschel ,  Andy Wei

    IPC: H01L21/84

    CPC classification number: H01L21/8221 ,  H01L21/823481 ,  H01L21/823835 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/66128 ,  H01L29/8611

    Abstract: A substrate diode for an SOI device is formed in accordance with an appropriately designed manufacturing flow, wherein transistor performance enhancing mechanisms may be implemented substantially without affecting the diode characteristics. In one aspect, respective openings for the substrate diode may be formed after the formation of a corresponding sidewall spacer structure used for defining the drain and source regions, thereby obtaining a significant lateral distribution of the dopants in the diode areas, which may therefore provide sufficient process margins during a subsequent silicidation sequence on the basis of a removal of the spacers in the transistor devices. In a further aspect, in addition to or alternatively, an offset spacer may be formed substantially without affecting the configuration of respective transistor devices.

    Abstract translation: 根据适当设计的制造流程形成用于SOI器件的衬底二极管，其中可以基本上实现晶体管性能增强机制而不影响二极管特性。 在一个方面，用于衬底二极管的相应开口可以在形成用于限定漏极和源极区域的相应的侧壁间隔结构形成之后形成，从而获得掺杂剂在二极管区域中的显着的横向分布，这可能因此提供足够的 基于去除晶体管器件中的间隔物，在随后的硅化序列期间的工艺余量。 在另一方面，除了或者可选地，可以基本上形成偏移间隔物而不影响各个晶体管器件的配置。

    REDUCING TRANSISTOR JUNCTION CAPACITANCE BY RECESSING DRAIN AND SOURCE REGIONS
    10.
    发明申请
    REDUCING TRANSISTOR JUNCTION CAPACITANCE BY RECESSING DRAIN AND SOURCE REGIONS 有权
    通过记录漏水和源区域降低晶体管结点电容

    公开(公告)号：US20100237431A1

    公开(公告)日：2010-09-23

    申请号：US12791290

    申请日：2010-06-01

    Applicant: Thomas Feudel ,  Markus Lenski ,  Andreas Gehring

    Inventor： Thomas Feudel ,  Markus Lenski ,  Andreas Gehring

    IPC: H01L27/092 ,  H01L21/336 ,  H01L21/8238

    CPC classification number: H01L21/324 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41733 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78621

    Abstract: By recessing portions of the drain and source areas on the basis of a spacer structure, the subsequent implantation process for forming the deep drain and source regions may result in a moderately high dopant concentration extending down to the buried insulating layer of an SOI transistor. Furthermore, the spacer structure maintains a significant amount of a strained semiconductor alloy with its original thickness, thereby providing an efficient strain-inducing mechanism. By using sophisticated anneal techniques, undue lateral diffusion may be avoided, thereby allowing a reduction of the lateral width of the respective spacers and thus a reduction of the length of the transistor devices. Hence, enhanced charge carrier mobility in combination with reduced junction capacitance may be accomplished on the basis of reduced lateral dimensions.

    Abstract translation: 通过基于间隔结构凹陷漏极和源极区域的部分，用于形成深漏极和源极区域的后续注入工艺可导致向下延伸到SOI晶体管的掩埋绝缘层的适度高的掺杂剂浓度。 此外，间隔结构保持大量的具有其原始厚度的应变半导体合金，从而提供有效的应变诱导机制。 通过使用复杂的退火技术，可以避免不适当的横向扩散，从而允许减小各个间隔物的横向宽度，从而减小晶体管器件的长度。 因此，可以基于减小的横向尺寸来实现增强的载流子迁移率与减少的结电容的组合。

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