公开(公告)号：US20090163186A1

公开(公告)日：2009-06-25

申请号：US11963136

申请日：2007-12-21

Applicant: Arvind Gupta ,  Ashutosh Tiwari ,  Gopalakrishnan Venkatraman ,  Dominic Cheung ,  Stacy R. Bennett ,  Douglas B. Koen

Inventor： Arvind Gupta ,  Ashutosh Tiwari ,  Gopalakrishnan Venkatraman ,  Dominic Cheung ,  Stacy R. Bennett ,  Douglas B. Koen

IPC: H04M3/42

CPC classification number: G06Q30/02

Abstract: Systems and methods for facilitating a review of mobile advertisement listings is provided. In one implementation, the method may include displaying information in a user interface for reviewing, the information associated with a mobile advertisement listing and at least one carrier, and at least one keyword associated with the mobile advertisement listing. The method may also include displaying in the user interface reviewing rules associated with a carrier for at least one carrier associated with the mobile advertisement listing and receiving an indication via the user interface of whether the mobile advertisement listing is approved for the carrier based on the displayed reviewing rules associated with the carrier.

Abstract translation: 提供了便于审查移动广告列表的系统和方法。 在一个实现中，该方法可以包括在用户界面中显示信息以查看与移动广告列表相关联的信息和至少一个运营商以及与移动广告列表相关联的至少一个关键字。 该方法还可以包括在用户界面中显示与用于与移动广告列表相关联的至少一个运营商的运营商相关联的规则，并且经由用户界面接收关于移动广告列表是否被批准用于运营商的指示 审查与运营商相关的规则。

公开(公告)号：US20080270668A1

公开(公告)日：2008-10-30

申请号：US12107274

申请日：2008-04-22

Applicant: Ashutosh Tiwari ,  Subrangshu Kumar Das

Inventor： Ashutosh Tiwari ,  Subrangshu Kumar Das

IPC: G06F13/28

CPC classification number: G06F13/4059

Abstract: A bus bridge between a high speed DMA bus and a lower speed peripheral bus sets a threshold for minimum available buffer space to send a read request dependent upon a frequency ratio and the DMA read latency. Similarly, a threshold for minimum available data for a write request depends on the frequency ratio and the DMA write latency. The bus bridge can store programmable values for the DMA read latency and write latency.

Abstract translation: 高速DMA总线和低速外设总线之间的总线桥接器设置最小可用缓冲区空间的阈值，以根据频率比和DMA读取延迟发送读取请求。 类似地，用于写请求的最小可用数据的阈值取决于频率比和DMA写延迟。 总线桥可以存储DMA读延迟和写延迟的可编程值。

公开(公告)号：US20060266442A1

公开(公告)日：2006-11-30

申请号：US11499352

申请日：2006-08-04

Applicant: Jagdish Narayan ,  Ashutosh Tiwari

Inventor： Jagdish Narayan ,  Ashutosh Tiwari

IPC: C22C21/00 ,  C23C4/08

CPC classification number: C23C28/04 ,  B82Y30/00 ,  B82Y40/00 ,  C23C14/024 ,  C23C14/0688 ,  C23C14/28

Abstract: Nanostructures and methods of making nanostructures having self-assembled nanodot arrays wherein nanodots are self-assembled in a matrix material due to the free energies of the nanodot material and/or differences in the Gibb's free energy of the nanodot materials and matrix materials.

Abstract translation: 纳米结构和制备具有自组装纳米点阵列的纳米结构的方法，其中纳米点由于纳米棒材料的自由能而自组装在基体材料中和/或纳米点材料和基质材料的吉布斯自由能的差异。

公开(公告)号：US07105118B2

公开(公告)日：2006-09-12

申请号：US10723842

申请日：2003-11-26

Applicant: Jagdish Narayan ,  Ashutosh Tiwari

Inventor： Jagdish Narayan ,  Ashutosh Tiwari

IPC: B82B3/00 ,  H01L21/4763

CPC classification number: H01F41/20 ,  B82Y10/00 ,  B82Y25/00 ,  G11B5/855 ,  H01F1/0063 ,  H01F1/009 ,  H01L29/127

Abstract: Nanostructures and methods of making nanostructures having self-assembled nanodot arrays wherein nanodots are self-assembled in a matrix material due to the free energies of the nanodot material and/or differences in the Gibb's free energy of the nanodot materials and matrix materials.

公开(公告)号：US20050182859A1

公开(公告)日：2005-08-18

申请号：US11034579

申请日：2005-01-13

Applicant: Subrangshu Das ,  Ashutosh Tiwari ,  Subash Govindarajan

Inventor： Subrangshu Das ,  Ashutosh Tiwari ,  Subash Govindarajan

IPC: G06F13/10 ,  G06F13/28

CPC classification number: G06F13/28 ,  G06F2213/0038

Abstract: A system-on-chip integrated circuit includes a peripheral initialization register has a bit corresponding to each module. Each bit indicates a normal mode or a reset mode for the corresponding module. A direct memory access unit can receive, prioritize and queue date movement transactions between modules and can read from or write to the peripheral initialization register. A peripheral interface unit prevents a write to the peripheral initialization register changing a module from reset mode to normal mode while there is an uncompleted data movement transaction involving that module. A false acknowledge circuit for each module supplies an acknowledge signal in response to a received command if the module is in reset mode.

Abstract translation: 片上系统集成电路包括外设初始化寄存器，其中每个模块都有一个位。 每个位表示相应模块的正常模式或复位模式。 直接存储器访问单元可以接收，优先排列和排队模块之间的日期移动事务，并且可以从外设初始化寄存器读取或写入外部初始化寄存器。 外围接口单元防止写周围初始化寄存器将模块从复位模式更改为正常模式，同时存在涉及该模块的未完成数据移动事务。 如果模块处于复位模式，每个模块的错误确认电路将响应于接收到的命令提供一个确认信号。