公开(公告)号：US07423453B1

公开(公告)日：2008-09-09

申请号：US11336014

申请日：2006-01-20

申请人： Benjamin S. Ting ,  Peter M. Pani

发明人： Benjamin S. Ting ,  Peter M. Pani

IPC分类号： H03K19/177

CPC分类号： H03K19/17736 ,  G06F17/5077 ,  H03K19/1778

摘要： Efficient layout schemes to implement switching networks of an interconnection fabric in an integrated circuit to connect two sets of conductors through rows of switches with prescribed number of tracks over the switching area are described. The layout schemes can be used repeatedly for multiple-stage switching network and/or hierarchically arranged switching networks.

摘要翻译： 描述了在集成电路中实现互连结构的交换网络的高效布局方案，以通过交换区域上具有规定数量的磁道的交换机行来连接两组导体。 布局方案可以重复使用于多级交换网络和/或分层布置的交换网络。

公开(公告)号：US07382156B2

公开(公告)日：2008-06-03

申请号：US11219597

申请日：2005-09-01

申请人： Peter M. Pani ,  Benjamin S. Ting

发明人： Peter M. Pani ,  Benjamin S. Ting

IPC分类号： H03K19/177

CPC分类号： H03K19/17704 ,  H03K19/17728 ,  H03K19/17732 ,  H03K19/17736 ,  H03K19/1776 ,  H03K19/1778 ,  H03K19/17796

摘要： An integrated circuit including a programmable logic array with a plurality of logic cells and programmable interconnections to receive input signals and to perform logical functions to transmit output signals. The integrated circuit may also include megacells comprising a plurality of functional blocks receiving inputs and transmitting outputs. The integrated circuit may also include a programmable interconnections subsystem to cascade the megacells. The megacells are coupled to the programmable logic array.

公开(公告)号：US07368943B2

公开(公告)日：2008-05-06

申请号：US11392411

申请日：2006-03-28

申请人： Peter M. Pani ,  Benjamin S. Ting

发明人： Peter M. Pani ,  Benjamin S. Ting

IPC分类号： H01L25/00 ,  H03K19/177

CPC分类号： H04Q3/521 ,  H03K17/002 ,  H03K19/17736 ,  H04Q2213/1302 ,  H04Q2213/1304 ,  H04Q2213/1332 ,  H04Q2213/13322

摘要： An interconnection fabric using switching networks organized in multiple levels of hierarchy to allow flexible interconnections of the switching networks amongst different levels of hierarchy and on the same level of hierarchy. The resulting interconnection fabric can be used in electronic devices, such as switching networks, routers, and programmable logic circuits, etc.

摘要翻译： 使用以多层次结构组织的交换网络的互连结构，以允许不同级别的层次结构和相同层级上的交换网络的灵活互连。 所形成的互连结构可以用于诸如交换网络，路由器和可编程逻辑电路等的电子设备中。

公开(公告)号：US07126375B2

公开(公告)日：2006-10-24

申请号：US11326543

申请日：2006-01-04

申请人： Benjamin S. Ting ,  Peter M. Pani

发明人： Benjamin S. Ting ,  Peter M. Pani

IPC分类号： G06F9/00

CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/17792 ,  H03K19/17796

摘要： A multiple level routing architecture for a programmable logic device having logical blocks, each logical block comprising a plurality of cells, with a first level routing resources coupling the cells of logical blocks. A second level routing resources coupling the first level routing resources through tab networks; each tab network comprises a first plurality of switches coupling the first level routing resources to an intermediate tab and the intermediate tab coupling the second level routing resources through a second plurality of switches, each switch may comprise an additional buffer. Repeated applications of tab networks provide connections between lower level routing resources to higher level routing resources.

摘要翻译： 具有逻辑块的可编程逻辑设备的多级路由架构，每个逻辑块包括多个小区，具有耦合逻辑块的小区的第一级路由资源。 第二级路由资源通过标签网络耦合第一级路由资源; 每个标签网络包括将第一级路由资源耦合到中间标签的第一多个交换机，以及通过第二多个交换机耦合第二级路由资源的中间标签，每个交换机可以包括附加缓冲器。 标签网络的重复应用提供了较低级别路由资源与较高级别路由资源之间的连接。

公开(公告)号：US07017136B2

公开(公告)日：2006-03-21

申请号：US10692880

申请日：2003-10-23

申请人： Benjamin S. Ting

发明人： Benjamin S. Ting

IPC分类号： G06F17/50

CPC分类号： H03K19/17704 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1778 ,  H03K19/17796

摘要： An architecture of hierarchical interconnect scheme for field programmable gate arrays (FPGAs). A first layer of routing network lines is used to provide connections amongst sets of block connectors where block connectors are used to provide connectability between logical cells and accessibility to the hierarchical routing network. A second layer of routing network lines provides connectability between different first layers of routing network lines. Additional layers of routing network lines are implemented to provide connectability between different prior layers of routing network lines. An additional routing layer is added when the number of cells is increased as the prior cell count in the array increases while the length of the routing lines and the number of routing lines also increases. Switching networks are used to provide connectability among same and different layers of routing network lines, each switching network composed primarily of program controlled passgates and, when needed, drivers.

摘要翻译： 用于现场可编程门阵列（FPGA）的分层互连方案架构。 第一层路由网络线路用于提供块连接器组之间的连接，其中块连接器用于提供逻辑单元之间的连接性和对分层路由网络的可访问性。 第二层路由网络线路提供不同第一层路由网络线路之间的连接性。 路由网络线路的附加层被实现以提供不同的现有路由网络线路之间的可连接性。 当阵列中的先前单元计数增加时，单元数量增加，而路由线路长度和路由线路数量也增加时，将添加一个额外的路由层。 交换网络用于在相同和不同层次的路由网络线路之间提供可连接性，每个交换网络主要由程序控制的门户组成，并且在需要时由驱动程序组成。

公开(公告)号：US07009422B2

公开(公告)日：2006-03-07

申请号：US10021744

申请日：2001-12-05

申请人： Benjamin S. Ting ,  Peter M. Pani

发明人： Benjamin S. Ting ,  Peter M. Pani

IPC分类号： G06F9/00

CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/17792 ,  H03K19/17796

摘要： A programmable logic device which incorporates an innovative routing hierarchy consisting of the multiple levels of routing lines, connector tab networks and turn matrices, enables an innovative, space saving floor plan to be utilized in an integrated circuit implementation, and is particularly efficient when an SRAM is used as the configuration bit This floor plan is a scalable block architecture in which each block connector tab networks of a 2×2 block grouping is arranged as a mirror image along the adjacent axis relative to each other. Furthermore, the bidirectional input/output lines are provided as the input/output means for each block are oriented only in two directions (instead of the typical north, south, east and west directions) such that the block connector tab networks for adjacent blocks face each other in orientation. This orientation and arrangement permits blocks to share routing resources. In addition, this arrangement enables a 4×4 block grouping to be scalable. The innovative floor plan makes efficient use of die space with little layout dead space as the floor plan provides for a plurality of contiguous memory and passgate arrays (which provide the functionality of the bidirectional switches) with small regions of logic for CFGs and drivers of the block connector tab networks. Therefore, the gaps typically incurred due to a mixture of memory and logic are avoided. Intra-cluster routing lines and bi-directional routing lines are overlayed on different layers of the chip together with memory and passgate arrays to provide connections to higher level routing lines and connections between CFGs in the block.

公开(公告)号：US06624658B2

公开(公告)日：2003-09-23

申请号：US10231320

申请日：2002-08-28

申请人： Peter M. Pani ,  Benjamin S. Ting

发明人： Peter M. Pani ,  Benjamin S. Ting

IPC分类号： H03K19177

CPC分类号： H03K19/17704 ,  H03K19/17728 ,  H03K19/17732 ,  H03K19/17736 ,  H03K19/1776 ,  H03K19/1778 ,  H03K19/17796

摘要： The system and method of the present invention provides an innovative bus system of lines which can be programmed and to provide data, control and address information to the logic circuits interconnected by the bus system. This flexible structure and process enables a configurable system to be created to programmably connect one or more logic circuits, such as megacells. The programmability of the bus system enables the cascading of multiple megacells in an arbitrary fashion (i.e., wide, deep or both) and the sharing of common lines for system level communication.

公开(公告)号：US06462578B2

公开(公告)日：2002-10-08

申请号：US09482149

申请日：2000-01-12

申请人： Benjamin S. Ting

发明人： Benjamin S. Ting

IPC分类号： H03K19177

CPC分类号： H03K19/17704 ,  H03K19/17728 ,  H03K19/17736

摘要： An architecture and distributed hierarchical interconnect scheme for field programmable gate arrays (FPGAs). The FPGA is comprised of a number of cells which perform logical functions on input signals. Programmable intraconnections provide connectability between each output of a cell belonging to a logical cluster to at least one input of each of the other cells belonging to that logical cluster. A set of programmable block connectors are used to provide connectability between logical clusters of cells and accessibility to the hierarchical routing network. An uniformly distributed first layer of routing network lines is used to provide connections amongst sets of block connectors. An uniformly distributed second layer of routing network lines is implemented to provide connectability between different first layers of routing network lines. Switching networks are used to provide connectability between the block connectors and routing network lines corresponding to the first layer. Other switching networks provide connectability between the routing network lines corresponding to the first layer to routing network lines corresponding to the second layer. Additional uniformly distributed layers of routing network lines are implemented to provide connectability between different prior layers of routing network lines. An additional routing layer is added when the number of cells is increased as a square function of two of the prior cell count in the array while the length of the routing lines and the number of routing lines increases as a linear function of two. Programmable bidirectional passgates are used as switches to control which of the routing network lines are to be connected.

摘要翻译： 用于现场可编程门阵列（FPGA）的架构和分布式分层互连方案。 FPGA由多个对输入信号执行逻辑功能的单元组成。 可编程的内连接将属于逻辑集群的小区的每个输出之间的连接性提供给属于该逻辑集群的每个其他小区的至少一个输入。 一组可编程块连接器用于提供单元的逻辑簇之间的可连接性以及对分层路由网络的可访问性。 使用均匀分布的第一层路由网络线路来提供块连接器组之间的连接。 实现均匀分布的第二层路由网络线路以提供不同第一层路由网络线路之间的可连接性。 交换网络用于提供块连接器与对应于第一层的路由网络线路之间的可连接性。 其他交换网络提供对应于第一层的路由网络线路与对应于第二层的路由网络线路之间的可连接性。 实现了额外的均匀分布的路由网络线路层以提供不同的现有路由网络线路之间的可连接性。 当单元的数量作为阵列中的两个先前单元计数的平方函数增加时，添加另外的路由层，而路由线的长度和路由线的数量增加为两个的线性函数。 可编程双向通行通道用作开关来控制要连接的路由网络线路。

公开(公告)号：US6051991A

公开(公告)日：2000-04-18

申请号：US909928

申请日：1997-08-12

申请人： Benjamin S. Ting

发明人： Benjamin S. Ting

IPC分类号： H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/17792 ,  H03K19/17796

摘要： An architecture and distributed hierarchical interconnect scheme for field programmable gate arrays (FPGAs). The FPGA is comprised of a number of cells which perform logical functions on input signals. Programmable intraconnections provide connectability between each output of a cell belonging to a logical cluster to at least one input of each of the other cells belonging to that logical cluster. A set of programmable block connectors are used to provide connectability between logical clusters of cells and accessibility to the hierarchical routing network. An uniformly distributed first layer of routing network lines is used to provide connections amongst sets of block connectors. An uniformly distributed second layer of routing network lines is implemented to provide connectability between different first layers of routing network lines. Switching networks are used to provide connectability between the block connectors and routing network lines corresponding to the first layer. Other switching networks provide connectability between the routing network lines corresponding to the first layer to routing network lines corresponding to the second layer. Additional uniformly distributed layers of routing network lines are implemented to provide connectability between different prior layers of routing network lines. An additional routing layer is added when the number of cells is increased as a square function of two of the prior cell count in the array while the length of the routing lines and the number of routing lines increases as a linear function of two. Programmable bi-directional passgates are used as switches to control which of the routing network lines are to be connected.

公开(公告)号：US5640327A

公开(公告)日：1997-06-17

申请号：US599122

申请日：1996-02-09

申请人： Benjamin S. Ting

发明人： Benjamin S. Ting

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： An apparatus and method for determining how to interconnect a plurality of components of a system, given a limited number of interconnect resources available to a device. First, it is determined whether the system meets the capacity constraints of the device. If the requirements exceed the capacity, a larger device is necessary. Otherwise, a topmost interconnection level is established. This topmost level is partitioned into four different partitions. The components are assigned and optimized to these four partitions. Next, a lower level of interconnection is established for one or more of these four partitions. Each of these lower levels are, in turn, partitioned into four different partitions. Components are then assigned and optimized to these partitions. This process is repeated for even lower levels until routing of the interconnections for the system is achieved. Thereupon, the components are physically interconnected from the lower levels to the topmost level according to the routing pattern that was determined in the establishing, partitioning, and said optimizing steps.

摘要翻译： 给定有限数量的可用于设备的互连资源的用于确定如何互连系统的多个组件的装置和方法。 首先，确定系统是否满足设备的容量限制。 如果要求超过容量，则需要较大的设备。 否则，建立最高的互连级别。 这个最上层分为四个不同的分区。 为这四个分区分配和优化组件。 接下来，为这四个分区中的一个或多个建立较低级别的互连。 这些较低级别中的每一个又分成四个不同的分区。 然后将组件分配并优化到这些分区。 对于甚至更低的级别重复该过程，直到实现用于系统的互连的路由。 因此，根据在建立，分区和所述优化步骤中确定的路由模式，组件从较低级别物理地互连到最高级别。