公开(公告)号：US20050050978A1

公开(公告)日：2005-03-10

申请号：US10704736

申请日：2003-11-12

Applicant: Byeong-Hoon Lee

Inventor： Byeong-Hoon Lee

IPC: B62D1/18 ,  B62D1/184 ,  B62D1/187

CPC classification number: B62D1/184

Abstract: The present invention relates to a tilt device for allowing a steering column to be tilted so that a driver can adjust the position of a steering wheel to conform to his/her figure in order to more comfortably drive a vehicle. The tilt device of the invention has an effect in that it can impart a high supporting strength to the steering column while reliably locking the same.

Abstract translation: 本发明涉及一种用于允许转向柱倾斜的倾斜装置，使得驾驶员可以调节方向盘的位置以符合他/她的身材，以便更舒适地驾驶车辆。 本发明的倾斜装置具有能够在可靠地锁定转向柱的同时赋予转向柱高的支撑强度的效果。

公开(公告)号：US20050007822A1

公开(公告)日：2005-01-13

申请号：US10880800

申请日：2004-06-30

Applicant: Byeong-hoon Lee ,  Chil-hee Chung

Inventor： Byeong-hoon Lee ,  Chil-hee Chung

IPC: G11C29/00 ,  G11C11/00 ,  G11C16/00 ,  G11C16/04 ,  G11C17/00 ,  H01L27/105 ,  G11C11/34

CPC classification number: G11C16/0425

Abstract: An integrated circuit memory device includes programmed memory cells and programmable and erasable memory cells. The memory device includes a first memory array block in which programmed memory cells are arranged and a second memory array block in which programmable and erasable memory cells are arranged. The programmed memory cells in the first memory array block may be programmed with predetermined data during a semiconductor manufacturing process, and may be mask read-only memory (ROM) cells. The programmable and erasable memory cells in the second memory array block may be programmed or erased with predetermined data after the semiconductor manufacturing process, and may be electrically erasable and programmable read-only memory (EEPROM) cells or flash memory cells.

Abstract translation: 集成电路存储器件包括编程存储器单元和可编程和可擦除存储器单元。 存储器件包括其中布置有编程存储器单元的第一存储器阵列块和布置可编程和可擦除存储器单元的第二存储器阵列块。 第一存储器阵列块中的编程存储单元可以在半导体制造过程期间用预定数据编程，并且可以是掩模只读存储器（ROM）单元。 第二存储器阵列块中的可编程和可擦除存储单元可以在半导体制造过程之后用预定数据进行编程或擦除，并且可以是电可擦除可编程只读存储器（EEPROM）单元或闪存单元。

公开(公告)号：US06442079B2

公开(公告)日：2002-08-27

申请号：US09765692

申请日：2001-01-19

Applicant: Byeong-Hoon Lee ,  Seung-Keun Lee

Inventor： Byeong-Hoon Lee ,  Seung-Keun Lee

IPC: G11C700

CPC classification number: G11C16/30

Abstract: A word line voltage generating circuit has a high voltage generator for generating a high voltage is response to an activation signal. In addition it has a regulator circuit that includes two successive regulators. The first regulator receives the high voltage and outputs an intermediate voltage in response to a reference voltage and the activation signal. The first regulator receives the reference voltage, and adjusts the high voltage to deliver a word line voltage. The second stage includes has a depletion-type NMOS transistor, which can clamp the high voltage to a voltage of a required level.

Abstract translation: 字线电压发生电路具有用于产生高电压的高电压发生器是对激活信号的响应。 此外，它具有包括两个连续调节器的调节器电路。 第一调节器接收高电压并响应于参考电压和激活信号输出中间电压。 第一个调节器接收参考电压，并调节高电压以输出字线电压。 第二级包括具有耗尽型NMOS晶体管，其可以将高电压钳位到所需电平的电压。

公开(公告)号：US09755702B2

公开(公告)日：2017-09-05

申请号：US14803590

申请日：2015-07-20

Applicant: Jong-Pil Cho ,  Il-Jong Song ,  Byeong-Hoon Lee

Inventor： Jong-Pil Cho ,  Il-Jong Song ,  Byeong-Hoon Lee

IPC: H04B5/00 ,  H04W52/18 ,  H04W52/48

CPC classification number: H04B5/0062 ,  H04B5/0031

Abstract: A method of operating a near field communication (NFC) device includes receiving, by the NFC device, a first signal from an NFC reader, transmitting, by the NFC device, a response to the first signal to the NFC reader and changing selectively, by the NFC device, a radio frequency (RF) configuration parameter associated with signal transmission operation during a signal transmission interval, based on determining whether the NFC reader recognizes the response.

公开(公告)号：US20120300548A1

公开(公告)日：2012-11-29

申请号：US13570960

申请日：2012-08-09

Applicant: BYEONG-HOON LEE ,  KI-HONG KIM ,  SEUNG-WON LEE ,  SUN-KWON KIM

Inventor： BYEONG-HOON LEE ,  KI-HONG KIM ,  SEUNG-WON LEE ,  SUN-KWON KIM

IPC: G11C16/04

CPC classification number: G11C16/0483

Abstract: A memory system includes a memory and a memory controller operating to control the memory. The memory includes a random accessible memory including a memory cell array operable in a random access mode, a NAND flash memory, and a selection circuit making the memory controller operate either one of the random accessible memory or the NAND flash memory.

Abstract translation: 存储器系统包括操作以控制存储器的存储器和存储器控制器。 存储器包括随机存取存储器，其包括以随机存取模式操作的存储单元阵列，NAND闪速存储器和使存储器控制器操作随机存取存储器或NAND闪速存储器之一的选择电路。

公开(公告)号：US07558121B2

公开(公告)日：2009-07-07

申请号：US11694473

申请日：2007-03-30

Applicant: Byeong-Hoon Lee

Inventor： Byeong-Hoon Lee

IPC: G11C11/34

CPC classification number: G11C16/30 ,  G11C5/147 ,  G11C16/22

Abstract: A flash memory device includes an array having memory cells arranged in rows and columns. A high voltage generator is configured to supply a high voltage to the array during a programming operation. Write buffers corresponding to selected memory cells drive the selected memory cells with a program voltage or a program-inhibition voltage in response to input data. Each write buffer consumes a dummy cell current when input data is program-inhibited data. A current-voltage conversion circuit connected to the write buffers through a common sensing line supplies a current to the write buffers as the dummy cell current through the common sensing line and outputs a voltage proportional to the current, supplied to the write buffers. A current sink circuit discharges a current from an output of the high voltage generator in response to a voltage output from the current-voltage conversion circuit.

Abstract translation: 闪速存储器件包括具有排列成行和列的存储单元的阵列。 高电压发生器被配置为在编程操作期间向阵列提供高电压。 对应于所选择的存储器单元的写缓冲器响应于输入数据以编程电压或编程禁止电压驱动所选存储单元。 当输入数据为程序禁止数据时，每个写入缓冲区消耗一个虚拟单元电流。 通过公共检测线连接到写入缓冲器的电流 - 电压转换电路通过公共检测线将电流作为虚拟单元电流提供给写入缓冲器，并输出与提供给写入缓冲器的电流成比例的电压。 电流吸收电路响应于来自电流 - 电压转换电路的电压输出，从高电压发生器的输出放电电流。

公开(公告)号：US07483303B2

公开(公告)日：2009-01-27

申请号：US11695132

申请日：2007-04-02

Applicant: Byeong-Hoon Lee

Inventor： Byeong-Hoon Lee

IPC: G11C16/04

CPC classification number: G11C16/12 ,  G11C5/145

Abstract: A flash memory device including: a memory cell array having memory cells arranged in rows and columns; and a high voltage generator configured to generate a high voltage supplied into a source line of the memory cell array during a programming operation. The high voltage generator operates to vary the high voltage along an amount of current supplied into the memory cell array during the programming operation.

Abstract translation: 一种闪速存储器件，包括：具有以行和列排列的存储单元的存储单元阵列; 以及高压发生器，其被配置为在编程操作期间产生提供给所述存储单元阵列的源极线的高电压。 高电压发生器操作以在编程操作期间沿供给到存储单元阵列的电流量改变高电压。

公开(公告)号：US20080117689A1

公开(公告)日：2008-05-22

申请号：US11695132

申请日：2007-04-02

Applicant: Byeong-Hoon Lee

Inventor： Byeong-Hoon Lee

IPC: G11C11/34

CPC classification number: G11C16/12 ,  G11C5/145

Abstract: A flash memory device including; a memory cell array having memory cells arranged in rows and columns; and a high voltage generator configured to generate a high voltage supplied into a source line of the memory cell array during a programming operation. The high voltage generator operates to vary the high voltage along an amount of current supplied into the memory cell array during the programming operation.

Abstract translation: 一种闪存装置，包括： 具有以行和列排列的存储单元的存储单元阵列; 以及高压发生器，其被配置为在编程操作期间产生提供给所述存储单元阵列的源极线的高电压。 高电压发生器操作以在编程操作期间沿供给到存储单元阵列的电流量改变高电压。

公开(公告)号：US20080117674A1

公开(公告)日：2008-05-22

申请号：US11694473

申请日：2007-03-30

Applicant: Byeong-Hoon Lee

Inventor： Byeong-Hoon Lee

IPC: G11C16/06

CPC classification number: G11C16/30 ,  G11C5/147 ,  G11C16/22

Abstract: A flash memory device includes an array having memory cells arranged in rows and columns. A high voltage generator is configured to supply a high voltage to the array during a programming operation. Write buffers corresponding to selected memory cells drive the selected memory cells with a program voltage or a program-inhibition voltage in response to input data. Each write buffer consumes a dummy cell current when input data is program-inhibited data. A current-voltage conversion circuit connected to the write buffers through a common sensing line supplies a current to the write buffers as the dummy cell current through the common sensing line and outputs a voltage proportional to the current, supplied to the write buffers. A current sink circuit discharges a current from an output of the high voltage generator in response to a voltage output from the current-voltage conversion circuit.

Abstract translation: 闪速存储器件包括具有排列成行和列的存储单元的阵列。 高电压发生器被配置为在编程操作期间向阵列提供高电压。 对应于所选择的存储器单元的写缓冲器响应于输入数据以编程电压或编程禁止电压驱动所选存储单元。 当输入数据为程序禁止数据时，每个写入缓冲区消耗一个虚拟单元电流。 通过公共检测线连接到写入缓冲器的电流 - 电压转换电路通过公共检测线将电流作为虚拟单元电流提供给写入缓冲器，并输出与提供给写入缓冲器的电流成比例的电压。 电流吸收电路响应于来自电流 - 电压转换电路的电压输出，从高电压发生器的输出放电电流。

公开(公告)号：US07134358B2

公开(公告)日：2006-11-14

申请号：US10649809

申请日：2003-08-28

Applicant: Byeong-Hoon Lee

Inventor： Byeong-Hoon Lee

IPC: B62D1/18

CPC classification number: B62D1/184 ,  B62D1/187

Abstract: The present invention relates, in general, to a tilt steering apparatus for a vehicle, and more specifically, to a tilt steering apparatus for a vehicle, capable of adjusting the angle of a steering column by engaging a movable gear with a fixed gear or disengaging the movable gear from the fixed gear, using a lock slider that does a rectilinear motion by an operation lever. If the lock slider is separated from the operation lever, even when the operation lever rotates, the lock slider does a rectilinear motion only. Hence, the lock slider and the movable gear can always make the line contact with each other. Through this line contact, the supporting rigidity and the abrasion resistance of components can be improved.

Abstract translation: 本发明一般涉及用于车辆的倾斜转向装置，更具体地，涉及一种用于车辆的倾斜转向装置，其能够通过将可动齿轮与固定齿轮啮合或分离来调节转向柱的角度 来自固定齿轮的可动齿轮，使用通过操作杆进行直线运动的锁定滑块。 如果锁定滑块与操作杆分离，即使操作杆旋转，锁定滑块只能进行直线运动。 因此，锁定滑块和可动齿轮总能使线路彼此接触。 通过该线接触，可以提高部件的支撑刚性和耐磨性。