公开(公告)号：US07102926B2

公开(公告)日：2006-09-05

申请号：US10880800

申请日：2004-06-30

Applicant: Byeong-hoon Lee ,  Chil-hee Chung

Inventor： Byeong-hoon Lee ,  Chil-hee Chung

IPC: G11C16/04

CPC classification number: G11C16/0425

Abstract: An integrated circuit memory device includes programmed memory cells and programmable and erasable memory cells. The memory device includes a first memory array block in which programmed memory cells are arranged and a second memory array block in which programmable and erasable memory cells are arranged. The programmed memory cells in the first memory array block may be programmed with predetermined data during a semiconductor manufacturing process, and may be mask read-only memory (ROM) cells. The programmable and erasable memory cells in the second memory array block may be programmed or erased with predetermined data after the semiconductor manufacturing process, and may be electrically erasable and programmable read-only memory (EEPROM) cells or flash memory cells.

Abstract translation: 集成电路存储器件包括编程存储器单元和可编程和可擦除存储器单元。 存储器件包括其中布置有编程存储器单元的第一存储器阵列块和布置可编程和可擦除存储器单元的第二存储器阵列块。 第一存储器阵列块中的编程存储单元可以在半导体制造过程期间用预定数据编程，并且可以是掩模只读存储器（ROM）单元。 第二存储器阵列块中的可编程和可擦除存储单元可以在半导体制造过程之后用预定数据进行编程或擦除，并且可以是电可擦除可编程只读存储器（EEPROM）单元或闪存单元。

公开(公告)号：US20050007822A1

公开(公告)日：2005-01-13

申请号：US10880800

申请日：2004-06-30

Applicant: Byeong-hoon Lee ,  Chil-hee Chung

Inventor： Byeong-hoon Lee ,  Chil-hee Chung

IPC: G11C29/00 ,  G11C11/00 ,  G11C16/00 ,  G11C16/04 ,  G11C17/00 ,  H01L27/105 ,  G11C11/34

CPC classification number: G11C16/0425

Abstract: An integrated circuit memory device includes programmed memory cells and programmable and erasable memory cells. The memory device includes a first memory array block in which programmed memory cells are arranged and a second memory array block in which programmable and erasable memory cells are arranged. The programmed memory cells in the first memory array block may be programmed with predetermined data during a semiconductor manufacturing process, and may be mask read-only memory (ROM) cells. The programmable and erasable memory cells in the second memory array block may be programmed or erased with predetermined data after the semiconductor manufacturing process, and may be electrically erasable and programmable read-only memory (EEPROM) cells or flash memory cells.

Abstract translation: 集成电路存储器件包括编程存储器单元和可编程和可擦除存储器单元。 存储器件包括其中布置有编程存储器单元的第一存储器阵列块和布置可编程和可擦除存储器单元的第二存储器阵列块。 第一存储器阵列块中的编程存储单元可以在半导体制造过程期间用预定数据编程，并且可以是掩模只读存储器（ROM）单元。 第二存储器阵列块中的可编程和可擦除存储单元可以在半导体制造过程之后用预定数据进行编程或擦除，并且可以是电可擦除可编程只读存储器（EEPROM）单元或闪存单元。

公开(公告)号：US07379332B2

公开(公告)日：2008-05-27

申请号：US11459547

申请日：2006-07-24

Applicant: Byeong-hoon Lee ,  Chil-hee Chung

Inventor： Byeong-hoon Lee ,  Chil-hee Chung

IPC: G11C11/34

CPC classification number: G11C16/0425

Abstract: An integrated circuit memory device includes programmed memory cells and programmable and erasable memory cells. The memory device includes a first memory array block in which programmed memory cells are arranged and a second memory array block in which programmable and erasable memory cells are arranged. The programmed memory cells in the first memory array block may be programmed with predetermined data during a semiconductor manufacturing process, and may be mask read-only memory (ROM) cells. The programmable and erasable memory cells in the second memory array block may be programmed or erased with predetermined data after the semiconductor manufacturing process, and may be electrically erasable and programmable read-only memory (EEPROM) cells or flash memory cells.

Abstract translation: 集成电路存储器件包括编程存储器单元和可编程和可擦除存储器单元。 存储器件包括其中布置有编程存储器单元的第一存储器阵列块和布置可编程和可擦除存储器单元的第二存储器阵列块。 第一存储器阵列块中的编程存储器单元可以在半导体制造过程期间用预定数据编程，并且可以是掩模只读存储器（ROM）单元。 第二存储器阵列块中的可编程和可擦除存储单元可以在半导体制造过程之后用预定数据进行编程或擦除，并且可以是电可擦除可编程只读存储器（EEPROM）单元或闪存单元。

公开(公告)号：US20060250844A1

公开(公告)日：2006-11-09

申请号：US11459547

申请日：2006-07-24

Applicant: Byeong-hoon Lee ,  Chil-hee Chung

Inventor： Byeong-hoon Lee ,  Chil-hee Chung

IPC: G11C16/04

CPC classification number: G11C16/0425

Abstract: An integrated circuit memory device includes programmed memory cells and programmable and erasable memory cells. The memory device includes a first memory array block in which programmed memory cells are arranged and a second memory array block in which programmable and erasable memory cells are arranged. The programmed memory cells in the first memory array block may be programmed with predetermined data during a semiconductor manufacturing process, and may be mask read-only memory (ROM) cells. The programmable and erasable memory cells in the second memory array block may be programmed or erased with predetermined data after the semiconductor manufacturing process, and may be electrically erasable and programmable read-only memory (EEPROM) cells or flash memory cells.

Abstract translation: 集成电路存储器件包括编程存储器单元和可编程和可擦除存储器单元。 存储器件包括其中布置有编程存储器单元的第一存储器阵列块和布置可编程和可擦除存储器单元的第二存储器阵列块。 第一存储器阵列块中的编程存储单元可以在半导体制造过程期间用预定数据编程，并且可以是掩模只读存储器（ROM）单元。 第二存储器阵列块中的可编程和可擦除存储单元可以在半导体制造过程之后用预定数据进行编程或擦除，并且可以是电可擦除可编程只读存储器（EEPROM）单元或闪存单元。

公开(公告)号：US20050007859A1

公开(公告)日：2005-01-13

申请号：US10873104

申请日：2004-06-21

Applicant: Hwi-taek Chung ,  Byeong-hoon Lee

Inventor： Hwi-taek Chung ,  Byeong-hoon Lee

IPC: G11C8/08 ,  G11C8/10 ,  G11C8/12 ,  G11C8/14 ,  G11C16/08 ,  G11C7/00

CPC classification number: G11C16/08 ,  G11C8/08 ,  G11C8/10 ,  G11C8/12 ,  G11C8/14

Abstract: A memory device includes a predecoder that receives a row address and responsively generates a plurality of memory block selection signals, a plurality of word line selection signals, a plurality of source line selection signals, and a plurality of sub-block selection signals including respective groups of signals that correspond to respective levels of a hierarchy of sub-blocks in a plurality of memory blocks. The device further includes a global decoder that receives the sub-block selection signals and responsively generates segment activation signals for respective segments of memory blocks that correspond to respective sub-blocks at a lowest level of the hierarchy of sub-blocks. A plurality of word line decoders are coupled to word lines of respective ones of plurality of the memory blocks, with each word line decoder configured to receive the segment activation signals, a memory block selection signal and the word line selection signals and to responsively generate word line signals on the word lines coupled thereto. A plurality of source line decoders are coupled to source lines of respective ones of the plurality of memory blocks, each source line decoder configured to receive the segment activation signals, with a memory block selection signal, and the source line selection signals and to responsively generate source line signals one the source lines coupled thereto.

Abstract translation: 一种存储装置，包括接收行地址并响应地产生多个存储块选择信号的预解码器，多个字线选择信号，多个源极线选择信号和包括各组的多个子块选择信号 的信号，其对应于多个存储块中的子块的层级的各个级别。 该设备还包括全局解码器，其接收子块选择信号，并且响应于生成对应于子块层级的最低级别处的相应子块的存储器块的各个段的段激活信号。 多个字线解码器被耦合到多个存储块中的各个字线的字线，每个字线解码器被配置为接收段激活信号，存储块选择信号和字线选择信号，并响应地产生字 在与其耦合的字线上的线信号。 多个源极线解码器被耦合到多个存储器块中的相应源的源极线，每个源极线解码器被配置为利用存储器块选择信号和源极线选择信号接收段激活信号，并且响应地产生 源极线将与其耦合的源极线信号一个。

公开(公告)号：US08108755B2

公开(公告)日：2012-01-31

申请号：US12010244

申请日：2008-01-23

Applicant: Seung-won Lee ,  Byeong-hoon Lee ,  Ki-hong Kim ,  Sun-kwon Kim

Inventor： Seung-won Lee ,  Byeong-hoon Lee ,  Ki-hong Kim ,  Sun-kwon Kim

IPC: G01F11/10 ,  G11C29/00

CPC classification number: G11C16/3431 ,  G06F11/1068 ,  G11C16/3418 ,  G11C2029/0411

Abstract: Example embodiments provide a method and apparatus of correcting error data due to charge loss within a non-volatile memory device including a plurality of memory cells. The method of correcting error data within the non-volatile memory devices may include detecting error data in a second data group by comparing a first data group read from memory cells in response to a first voltage with the second data group read from memory cells in response to a second voltage. The second voltage is higher than the first voltage. Error data in the first data group is detected by error-correcting code (ECC). Re-writing data in the memory cells is performed by correcting error data in the first data group and error data in the second data group. A central processing unit (CPU) may detect error in the second data group. The second data group may be read through a page buffer and compared with the first data group stored in a SRAM. The detected error may be updated to the page buffer. Error data in the first data group may be updated to the page buffer. The CPU corrects error in the final error data, and the page buffer rewrites the corrected data in the plurality of memory cells.

Abstract translation: 示例性实施例提供了一种在包括多个存储器单元的非易失性存储器件内由于电荷损失而校正误差数据的方法和装置。 校正非易失性存储器件中的错误数据的方法可以包括通过将响应于第一电压的存储器单元读取的第一数据组与从存储器单元读取的第二数据组进行响应来检测第二数据组中的错误数据 到第二电压。 第二电压高于第一电压。 通过纠错码（ECC）检测第一数据组中的错误数据。 通过对第一数据组中的错误数据和第二数据组中的错误数据进行校正，来重新写入存储器单元中的数据。 中央处理单元（CPU）可以检测第二数据组中的错误。 可以通过页缓冲器读取第二数据组，并与存储在SRAM中的第一数据组进行比较。 检测到的错误可能更新到页面缓冲区。 第一个数据组中的错误数据可能更新到页面缓冲区。 CPU更正最终错误数据中的错误，并且页缓冲区重写多个存储单元中的校正数据。

公开(公告)号：US07035162B2

公开(公告)日：2006-04-25

申请号：US10873104

申请日：2004-06-21

Applicant: Hwi-taek Chung ,  Byeong-hoon Lee

Inventor： Hwi-taek Chung ,  Byeong-hoon Lee

IPC: G11C8/00

CPC classification number: G11C16/08 ,  G11C8/08 ,  G11C8/10 ,  G11C8/12 ,  G11C8/14

Abstract: A memory device includes a predecoder that receives a row address and responsively generates a plurality of memory block selection signals, a plurality of word line selection signals, a plurality of source line selection signals, and a plurality of sub-block selection signals including respective groups of signals that correspond to respective levels of a hierarchy of sub-blocks in a plurality of memory blocks. The device further includes a global decoder that receives the sub-block selection signals and responsively generates segment activation signals for respective segments of memory blocks that correspond to respective sub-blocks at a lowest level of the hierarchy of sub-blocks. A plurality of word line decoders are coupled to word lines of respective ones of plurality of the memory blocks, with each word line decoder configured to receive the segment activation signals, a memory block selection signal and the word line selection signals and to responsively generate word line signals on the word lines coupled thereto. A plurality of source line decoders are coupled to source lines of respective ones of the plurality of memory blocks, each source line decoder configured to receive the segment activation signals, with a memory block selection signal, and the source line selection signals and to responsively generate source line signals one the source lines coupled thereto.

Abstract translation: 一种存储装置，包括接收行地址并响应地产生多个存储块选择信号的预解码器，多个字线选择信号，多个源极线选择信号和包括各组的多个子块选择信号 的信号，其对应于多个存储块中的子块的层级的各个级别。 该设备还包括全局解码器，其接收子块选择信号，并且响应于生成对应于子块层级的最低级别处的相应子块的存储器块的各个段的段激活信号。 多个字线解码器被耦合到多个存储块中的各个字线的字线，每个字线解码器被配置为接收段激活信号，存储块选择信号和字线选择信号，并响应地产生字 在与其耦合的字线上的线信号。 多个源极线解码器被耦合到多个存储器块中的相应源的源极线，每个源极线解码器被配置为利用存储器块选择信号和源极线选择信号接收段激活信号，并且响应地产生 源极线将与其耦合的源极线信号一个。

公开(公告)号：US08659394B2

公开(公告)日：2014-02-25

申请号：US13093254

申请日：2011-04-25

Applicant: Il-jong Song ,  Byeong-hoon Lee ,  Seung-won Lee ,  Chul-joon Choi

Inventor： Il-jong Song ,  Byeong-hoon Lee ,  Seung-won Lee ,  Chul-joon Choi

IPC: H04Q5/22 ,  H04L5/12 ,  H03D3/02

CPC classification number: G06K19/07771 ,  H04Q2213/095

Abstract: Provided are a Radio Frequency IDentification (RFID) tag with a signal reception method. The RFID tag includes a demodulator that receives a read signal containing read data. The demodulator includes; a voltage generating circuit that provides a first voltage signal and a second voltage signal derived from the received read signal, an inverter that provides a data pulse signal indicative of the read data by inverting the second voltage signal using an inverting voltage defined in relation to the first voltage signal, and a buffer that recovers the read data by buffering the data pulse signal.

Abstract translation: 提供了具有信号接收方法的射频识别（RFID）标签。 RFID标签包括接收包含读取数据的读取信号的解调器。 解调器包括： 电压产生电路，其提供从所接收的读取信号导出的第一电压信号和第二电压信号;反相器，其通过使用相对于所述读取信号定义的反相电压来反转所述第二电压信号来提供指示所述读取数据的数据脉冲信号 第一电压信号和通过缓冲数据脉冲信号来恢复读取数据的缓冲器。

公开(公告)号：US20060114072A1

公开(公告)日：2006-06-01

申请号：US11289286

申请日：2005-11-30

Applicant: Seung-won Lee ,  Hwi-taek Chung ,  Byeong-hoon Lee

Inventor： Seung-won Lee ,  Hwi-taek Chung ,  Byeong-hoon Lee

IPC: H03K3/03

CPC classification number: H03L7/0995 ,  H03K3/00 ,  H03K3/0315 ,  H03K17/00 ,  H03L7/0802 ,  H03L7/18

Abstract: Methods and apparatuses for changing capacitance are provided. The apparatus may adjust a current supplied to a load capacitor according to the frequency of an input clock signal. When operating at a lower frequency, a capacitance may be increased such that noise immunity may be increased. When operating at a higher frequency, a capacitance may be decreased such that current consumption may be reduced.

Abstract translation: 提供了改变电容的方法和装置。 该装置可以根据输入时钟信号的频率调节提供给负载电容器的电流。 当以较低的频率操作时，可以增加电容，使得可以增加抗噪声性。 当以更高的频率工作时，可以减小电容，从而可以降低电流消耗。

公开(公告)号：US07298190B2

公开(公告)日：2007-11-20

申请号：US11247938

申请日：2005-10-11

Applicant: Seung-won Lee ,  Hwi-taek Chung ,  Byeong-hoon Lee

Inventor： Seung-won Lee ,  Hwi-taek Chung ,  Byeong-hoon Lee

IPC: H03L7/06

CPC classification number: H03L7/0995 ,  H03L7/0891 ,  H03L7/099 ,  H03L7/10 ,  H03L7/18 ,  H03L2207/06

Abstract: A phase locked loop (PLL) integrated circuit includes a voltage-controlled oscillator (VCO) configured to generate a clock signal at an output terminal thereof. The VCO is further configured to improve the frequency response of the PLL by varying a capacitance of the output terminal concurrently with changing a frequency of the clock signal. The VCO may include a control signal generator, which is configured to generate a plurality of control signals in response to UP and DOWN pumping signals, and an oscillator, which is configured to generate the clock signal in response to the plurality of control signals. The oscillator may be a ring oscillator, which is responsive to the plurality of control signals.

Abstract translation: 锁相环（PLL）集成电路包括被配置为在其输出端产生时钟信号的压控振荡器（VCO）。 VCO还被配置为通过改变输出端的电容同时改变时钟信号的频率来改善PLL的频率响应。 VCO可以包括控制信号发生器，其被配置为响应于UP和DOWN泵浦信号而产生多个控制信号，以及振荡器，其被配置为响应于多个控制信号而产生时钟信号。 振荡器可以是响应于多个控制信号的环形振荡器。