公开(公告)号：US20060019444A1

公开(公告)日：2006-01-26

申请号：US10895881

申请日：2004-07-21

申请人： Hsiang-Tai Lu ,  Cheng-Hsiung Kuo ,  Chin-Huang Wang

发明人： Hsiang-Tai Lu ,  Cheng-Hsiung Kuo ,  Chin-Huang Wang

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L21/28273 ,  H01L27/115 ,  H01L27/11521

摘要： A method of embedding the forming of peripheral devices such as HV-LDMOS into the forming of flash memory is presented. A layered structure is formed with a first insulating layer formed on a substrate, and a poly silicon formed on the first insulating layer in the flash memory region. A mask layer is formed. Openings are formed in the flash memory region in the peripheral region. A local oxidation of silicon (LOCOS) is performed to form thick oxides on poly silicon, and a field oxide on silicon substrate respectively. The mask layer is removed. A control gate and a control gate oxide are formed on the thick oxide and the poly silicon. A gate electrode is formed with at least one end residing on a field oxide so that the resulting HV-LDMOS has a high breakdown voltage. Spacers and a source/drain of the flash cells and HV-LDMOSs are then formed.

摘要翻译： 提出了一种将诸如HV-LDMOS之类的外围设备的形成嵌入到闪速存储器的形成中的方法。 层叠结构形成有在基板上形成的第一绝缘层，以及形成在闪存区域中的第一绝缘层上的多晶硅。 形成掩模层。 开口形成在周边区域的闪存区域中。 进行硅的局部氧化（LOCOS）以在多晶硅上形成厚氧化物，分别在硅衬底上形成场氧化物。 去除掩模层。 在厚氧化物和多晶硅上形成控制栅极和控制栅极氧化物。 栅电极形成有驻留在场氧化物上的至少一端，使得所得的HV-LDMOS具有高的击穿电压。 然后形成闪存单元和HV-LDMOS的间隔物和源极/漏极。

公开(公告)号：US20050232048A1

公开(公告)日：2005-10-20

申请号：US10826457

申请日：2004-04-16

申请人： Cheng-Hsiung Kuo

发明人： Cheng-Hsiung Kuo

IPC分类号： G11C7/00 ,  G11C7/22 ,  G11C8/08 ,  G11C11/00 ,  G11C16/32

CPC分类号： G11C16/32 ,  G11C7/22 ,  G11C8/08

摘要： An improved memory device and the method for programming the same are disclosed. The memory device includes at least one memory block requiring a word line pre-charge time to be long enough to program one or more selected memory cells. A monitoring circuit is added for detecting one or more word lines to reach a predetermined threshold voltage to enable a predetermined high voltage to be supplied to one or more latches of the memory cells.

摘要翻译： 公开了一种改进的存储器件及其编程方法。 存储器件包括至少一个需要字线预充电时间足以对一个或多个所选择的存储器单元进行编程的存储器块。 添加监视电路，用于检测一个或多个字线以达到预定的阈值电压，以使预定的高电压能够提供给存储器单元的一个或多个锁存器。

公开(公告)号：US06498737B1

公开(公告)日：2002-12-24

申请号：US10050445

申请日：2002-01-16

申请人： Cheng-Hsiung Kuo

发明人： Cheng-Hsiung Kuo

IPC分类号： H02M318

CPC分类号： G05F3/242 ,  H02M3/073 ,  H02M2003/078

摘要： This invention provides a circuit and a method for regulating the voltage of semiconductor integrated circuits. It provides the ability to accurately regulate voltage on chips by eliminating the sensitivity due to temperature, process and noise by eliminating the problems introduced by body effect. The invention utilizes a charge pump, a PN diode, diode connected NMOS field effect transistors, one or more intrinsic NMOS field effect transistors, a current mirror discharge NMOS field effect transistor, a current source and, a diode connected NMOS field effect transistor current mirror.

摘要翻译： 本发明提供一种用于调节半导体集成电路的电压的电路和方法。 通过消除由身体效应引起的问题，通过消除由于温度，过程和噪音引起的灵敏度，可以精确调节芯片上的电压。 本发明利用电荷泵，PN二极管，二极管连接的NMOS场效应晶体管，一个或多个本征NMOS场效应晶体管，电流镜放电NMOS场效应晶体管，电流源和二极管连接的NMOS场效应晶体管电流镜 。