公开(公告)号：US20070296022A1

公开(公告)日：2007-12-27

申请号：US11848066

申请日：2007-08-30

申请人： Hsiang-Tai Lu ,  Cheng-Hsiung Kuo ,  Chin-Huang Wang

发明人： Hsiang-Tai Lu ,  Cheng-Hsiung Kuo ,  Chin-Huang Wang

IPC分类号： H01L29/788

CPC分类号： H01L21/28273 ,  H01L27/115 ,  H01L27/11521

摘要： A method of embedding the forming of peripheral devices such as HV-LDMOS into the forming of flash memory is presented. A layered structure is formed with a first insulating layer formed on a substrate, and a poly silicon formed on the first insulating layer in the flash memory region. A mask layer is formed. Openings are formed in the flash memory region in the peripheral region. A local oxidation of silicon (LOCOS) is performed to form thick oxides on poly silicon, and a field oxide on silicon substrate respectively. The mask layer is removed. A control gate and a control gate oxide are formed on the thick oxide and the poly silicon. A gate electrode is formed with at least one end residing on a field oxide so that the resulting HV-LDMOS has a high breakdown voltage. Spacers and a source/drain of the flash cells and HV-LDMOSs are then formed.

摘要翻译： 提出了一种将诸如HV-LDMOS之类的外围设备的形成嵌入到闪速存储器的形成中的方法。 层叠结构形成有在基板上形成的第一绝缘层，以及形成在闪存区域中的第一绝缘层上的多晶硅。 形成掩模层。 开口形成在周边区域的闪存区域中。 进行硅的局部氧化（LOCOS）以在多晶硅上形成厚氧化物，分别在硅衬底上形成场氧化物。 去除掩模层。 在厚氧化物和多晶硅上形成控制栅极和控制栅极氧化物。 栅电极形成有驻留在场氧化物上的至少一端，使得所得的HV-LDMOS具有高的击穿电压。 然后形成闪存单元和HV-LDMOS的间隔物和源极/漏极。

公开(公告)号：US07282410B2

公开(公告)日：2007-10-16

申请号：US10895881

申请日：2004-07-21

申请人： Hsiang-Tai Lu ,  Cheng-Hsiung Kuo ,  Chin-Huang Wang

发明人： Hsiang-Tai Lu ,  Cheng-Hsiung Kuo ,  Chin-Huang Wang

IPC分类号： H01L21/8247

CPC分类号： H01L21/28273 ,  H01L27/115 ,  H01L27/11521

摘要： A method of embedding the forming of peripheral devices such as HV-LDMOS into the forming of flash memory is presented. A layered structure is formed with a first insulating layer formed on a substrate, and a poly silicon formed on the first insulating layer in the flash memory region. A mask layer is formed. Openings are formed in the flash memory region in the peripheral region. A local oxidation of silicon (LOCOS) is performed to form thick oxides on poly silicon, and a field oxide on silicon substrate respectively. The mask layer is removed. A control gate and a control gate oxide are formed on the thick oxide and the poly silicon. A gate electrode is formed with at least one end residing on a field oxide so that the resulting HV-LDMOS has a high breakdown voltage. Spacers and a source/drain of the flash cells and HV-LDMOSs are then formed.

摘要翻译： 提出了一种将诸如HV-LDMOS之类的外围设备的形成嵌入到闪速存储器的形成中的方法。 层叠结构形成有在基板上形成的第一绝缘层，以及形成在闪存区域中的第一绝缘层上的多晶硅。 形成掩模层。 开口形成在周边区域的闪存区域中。 进行硅的局部氧化（LOCOS）以在多晶硅上形成厚氧化物，分别在硅衬底上形成场氧化物。 去除掩模层。 在厚氧化物和多晶硅上形成控制栅极和控制栅极氧化物。 栅电极形成有驻留在场氧化物上的至少一端，使得所得的HV-LDMOS具有高的击穿电压。 然后形成闪存单元和HV-LDMOS的间隔物和源极/漏极。

公开(公告)号：US20060019444A1

公开(公告)日：2006-01-26

申请号：US10895881

申请日：2004-07-21

申请人： Hsiang-Tai Lu ,  Cheng-Hsiung Kuo ,  Chin-Huang Wang

发明人： Hsiang-Tai Lu ,  Cheng-Hsiung Kuo ,  Chin-Huang Wang

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L21/28273 ,  H01L27/115 ,  H01L27/11521

摘要： A method of embedding the forming of peripheral devices such as HV-LDMOS into the forming of flash memory is presented. A layered structure is formed with a first insulating layer formed on a substrate, and a poly silicon formed on the first insulating layer in the flash memory region. A mask layer is formed. Openings are formed in the flash memory region in the peripheral region. A local oxidation of silicon (LOCOS) is performed to form thick oxides on poly silicon, and a field oxide on silicon substrate respectively. The mask layer is removed. A control gate and a control gate oxide are formed on the thick oxide and the poly silicon. A gate electrode is formed with at least one end residing on a field oxide so that the resulting HV-LDMOS has a high breakdown voltage. Spacers and a source/drain of the flash cells and HV-LDMOSs are then formed.

摘要翻译： 提出了一种将诸如HV-LDMOS之类的外围设备的形成嵌入到闪速存储器的形成中的方法。 层叠结构形成有在基板上形成的第一绝缘层，以及形成在闪存区域中的第一绝缘层上的多晶硅。 形成掩模层。 开口形成在周边区域的闪存区域中。 进行硅的局部氧化（LOCOS）以在多晶硅上形成厚氧化物，分别在硅衬底上形成场氧化物。 去除掩模层。 在厚氧化物和多晶硅上形成控制栅极和控制栅极氧化物。 栅电极形成有驻留在场氧化物上的至少一端，使得所得的HV-LDMOS具有高的击穿电压。 然后形成闪存单元和HV-LDMOS的间隔物和源极/漏极。

公开(公告)号：US07462906B2

公开(公告)日：2008-12-09

申请号：US11848066

申请日：2007-08-30

申请人： Hsiang-Tai Lu ,  Cheng-Hsiung Kuo ,  Chin-Huang Wang

发明人： Hsiang-Tai Lu ,  Cheng-Hsiung Kuo ,  Chin-Huang Wang

IPC分类号： H01L29/788

CPC分类号： H01L21/28273 ,  H01L27/115 ,  H01L27/11521

摘要： A method of embedding the forming of peripheral devices such as HV-LDMOS into the forming of flash memory is presented. A layered structure is formed with a first insulating layer formed on a substrate, and a poly silicon formed on the first insulating layer in the flash memory region. A mask layer is formed. Openings are formed in the flash memory region in the peripheral region. A local oxidation of silicon (LOCOS) is performed to form thick oxides on poly silicon, and a field oxide on silicon substrate respectively. The mask layer is removed. A control gate and a control gate oxide are formed on the thick oxide and the poly silicon. A gate electrode is formed with at least one end residing on a field oxide so that the resulting HV-LDMOS has a high breakdown voltage. Spacers and a source/drain of the flash cells and HV-LDMOSs are then formed.

摘要翻译： 提出了一种将诸如HV-LDMOS之类的外围设备的形成嵌入到闪速存储器的形成中的方法。 层叠结构形成有在基板上形成的第一绝缘层，以及形成在闪存区域中的第一绝缘层上的多晶硅。 形成掩模层。 开口形成在周边区域的闪存区域中。 进行硅的局部氧化（LOCOS）以在多晶硅上形成厚氧化物，分别在硅衬底上形成场氧化物。 去除掩模层。 在厚氧化物和多晶硅上形成控制栅极和控制栅极氧化物。 栅电极形成有驻留在场氧化物上的至少一端，使得所得的HV-LDMOS具有高的击穿电压。 然后形成闪存单元和HV-LDMOS的间隔物和源极/漏极。

公开(公告)号：US20080024164A1

公开(公告)日：2008-01-31

申请号：US11496254

申请日：2006-07-31

申请人： Hsiang-Tai Lu ,  Cheng-Hsiung Kuo ,  Yue-Der Chih

发明人： Hsiang-Tai Lu ,  Cheng-Hsiung Kuo ,  Yue-Der Chih

IPC分类号： H03K19/177

CPC分类号： H03K19/1776 ,  H03K19/1778

摘要： A system is disclosed for constructing a reconfigurable programmable logic device (PLD) comprising a first P-channel nonvolatile memory cell with a first source, a first drain and a first gate coupled to a first input node, a second P-channel nonvolatile memory cell with a second source, a second drain and a second gate coupled to a second input node, and an NMOS transistor with a third source and a third drain, wherein the first and second sources are commonly connected to a positive voltage supply (Vcc), the first, second and third drains are commonly connected to an output node and the third source is coupled to a complementary low voltage supply (Vss).

摘要翻译： 公开了一种用于构造可重构可编程逻辑器件（PLD）的系统，该可重构可编程逻辑器件（PLD）包括具有第一源极，第一漏极和耦合到第一输入节点的第一栅极的第一P沟道非易失性存储器单元，第二P沟道非易失性存储单元 具有第二源极，耦合到第二输入节点的第二漏极和第二栅极，以及具有第三源极和第三漏极的NMOS晶体管，其中所述第一和第二源极共同连接到正电压源（Vcc） 第一，第二和第三漏极通常连接到输出节点，并且第三源耦合到互补的低电压源（Vss）。

公开(公告)号：US20070155092A1

公开(公告)日：2007-07-05

申请号：US11319357

申请日：2005-12-29

申请人： Hsiang-Tai Lu ,  Cheng-Hsiung Kuo ,  Yue-Der Chih

发明人： Hsiang-Tai Lu ,  Cheng-Hsiung Kuo ,  Yue-Der Chih

IPC分类号： H01L21/336 ,  H01L21/3205

CPC分类号： H01L29/7881 ,  H01J9/025 ,  H01L27/0207 ,  H01L29/40114

摘要： A method for forming a tip is disclosed. A layer is formed overlying a substrate. A mask layer is formed overlying the layer. The mask is patterned to form a mask pattern comprising an inner portion and an outer portion, wherein the inner portion is surrounded by the outer portion. The layer uncovered by the mask pattern is treated to form a reaction mask, wherein at least one portion of the reaction mask connect to form a tip of the layer under the inner portion of the mask pattern.

摘要翻译： 公开了一种用于形成尖端的方法。 层叠在衬底上方。 形成覆盖层的掩模层。 将掩模图案化以形成包括内部部分和外部部分的掩模图案，其中内部部分被外部部分包围。 处理由掩模图案覆盖的层以形成反应掩模，其中反应掩模的至少一部分连接以在掩模图案的内部部分的下方形成该顶层。

公开(公告)号：US07348832B2

公开(公告)日：2008-03-25

申请号：US11384846

申请日：2006-03-20

申请人： Hsiang-Tai Lu ,  Cheng-Hsiung Kuo ,  Yue-Der Chih

发明人： Hsiang-Tai Lu ,  Cheng-Hsiung Kuo ,  Yue-Der Chih

IPC分类号： G05F1/10

CPC分类号： G11C5/145 ,  G11C16/30

摘要： A voltage generation system for generating operating voltages for memory devices, especially non-volatile memories, from a single external high voltage source. In one embodiment, the system comprises an input terminal for receiving an external voltage, a charge pump for producing a first high voltage based on the external voltage to be higher than the external voltage, a first regulating circuit for regulating the first high voltage to a lower predetermined voltage, a second regulating circuit for generating a second high voltage based on the external voltage to be lower than the external voltage.

摘要翻译： 一种用于从单个外部高压源产生用于存储器件，尤其是非易失性存储器的工作电压的电压产生系统。 在一个实施例中，系统包括用于接收外部电压的输入端子，用于基于外部电压产生高于外部电压的第一高电压的电荷泵，用于将第一高电压调节到第一高电压的第一调节电路 降低预定电压，第二调节电路，用于基于外部电压产生低于外部电压的第二高电压。

公开(公告)号：US20070216471A1

公开(公告)日：2007-09-20

申请号：US11384846

申请日：2006-03-20

申请人： Hsiang-Tai Lu ,  Cheng-Hsiung Kuo ,  Yue-Der Chih

发明人： Hsiang-Tai Lu ,  Cheng-Hsiung Kuo ,  Yue-Der Chih

IPC分类号： G05F1/10

CPC分类号： G11C5/145 ,  G11C16/30

摘要： A voltage generation system for generating operating voltages for memory devices, especially non-volatile memories, from a single external high voltage source. In one embodiment, the system comprises an input terminal for receiving an external voltage, a charge pump for producing a first high voltage based on the external voltage to be higher than the external voltage, a first regulating circuit for regulating the first high voltage to a lower predetermined voltage, a second regulating circuit for generating a second high voltage based on the external voltage to be lower than the external voltage.

摘要翻译： 一种用于从单个外部高压源产生用于存储器件，尤其是非易失性存储器的工作电压的电压产生系统。 在一个实施例中，系统包括用于接收外部电压的输入端子，用于基于外部电压产生高于外部电压的第一高电压的电荷泵，用于将第一高电压调节到第一高电压的第一调节电路 降低预定电压，第二调节电路，用于基于外部电压产生低于外部电压的第二高电压。

公开(公告)号：US06958939B2

公开(公告)日：2005-10-25

申请号：US10663425

申请日：2003-09-15

申请人： Chia-Ta Hsieh ,  Chin-Huang Wang ,  I-Ming Chang ,  Hsiang-Tai Lu

发明人： Chia-Ta Hsieh ,  Chin-Huang Wang ,  I-Ming Chang ,  Hsiang-Tai Lu

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/10 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC分类号： G11C16/0425 ,  G11C16/0466 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7885

摘要： A flash memory cell of an EEPROM split-gate flash memory, the memory cell including a substrate having a plurality of active regions, and a floating gate structure disposed over the substrate. The floating gate structure extends across at least three of the active regions of the substrate such that the floating gate structure and the at least three active regions define at least two channel regions dedicated for programming.

摘要翻译： EEPROM分离栅闪存的快闪存储器单元，该存储单元包括具有多个有源区的衬底，以及设置在衬底上的浮栅结构。 浮置栅极结构延伸穿过衬底的有源区域中的至少三个，使得浮动栅极结构和至少三个有源区域限定专用于编程的至少两个沟道区域。

公开(公告)号：US20050057971A1

公开(公告)日：2005-03-17

申请号：US10663425

申请日：2003-09-15

申请人： Chia-Ta Hsieh ,  Chin-Huang Wang ,  I-Ming Chang ,  Hsiang-Tai Lu

发明人： Chia-Ta Hsieh ,  Chin-Huang Wang ,  I-Ming Chang ,  Hsiang-Tai Lu

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/10 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC分类号： G11C16/0425 ,  G11C16/0466 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7885

摘要： A flash memory cell of an EEPROM split-gate flash memory, the memory cell including a substrate having a plurality of active regions, and a floating gate structure disposed over the substrate. The floating gate structure extends across at least three of the active regions of the substrate such that the floating gate structure and the at least three active regions define at least two channel regions dedicated for programming.