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    DEVICE WITH MULTIPLE ROOTS OF TRUST
    41.
    发明申请
    DEVICE WITH MULTIPLE ROOTS OF TRUST 审中-公开

    公开(公告)号：US20180357183A1

    公开(公告)日：2018-12-13

    申请号：US15780005

    申请日：2016-12-01

    Applicant: CRYPTOGRAPHY RESEARCH, INC.

    Inventor： Ambuj KUMAR ,  William Craig RAWLINGS

    IPC: G06F12/14 ,  H04L9/08

    CPC classification number: G06F12/1408 ,  G06F21/57 ,  G06F21/6281 ,  G06F2212/1052 ,  G06F2221/2145 ,  H04L9/088 ,  H04L9/0897 ,  H04L9/3247 ,  H04L63/00 ,  H04L63/10 ,  H04L63/126

    Abstract: A container from a first root of trust associated with a first root entity may be received. The container may correspond to a mapping of a resource of an integrated circuit that is associated with the first root entity. The container may be verified based on a key that corresponds to the first root of trust and that is stored in the integrated circuit at manufacturing of the integrated circuit. An identification may be made that an assignment of the resource from the container corresponds to assigning the resource from the first root of trust to a new root of trust. A new key corresponding to the new root of trust may be generated. Information corresponding to the new key may be stored into a memory of the integrated circuit. Furthermore, the new key may be used to delegate the resource to a subsequent container.

    CRYPTOGRAPHIC MANAGEMENT OF LIFECYCLE STATES
    42.
    发明申请
    CRYPTOGRAPHIC MANAGEMENT OF LIFECYCLE STATES 审中-公开

    公开(公告)号：US20180248688A1

    公开(公告)日：2018-08-30

    申请号：US15755274

    申请日：2016-12-15

    Applicant: Cryptography Research, Inc

    Inventor： Ambuj KUMAR ,  Ronald PEREZ

    IPC: H04L9/08

    CPC classification number: H04L9/0861 ,  G09C1/00 ,  H04L9/085 ,  H04L9/0891

    Abstract: A secret key value that is inaccessible to software is scrambled according to registers consisting of one-time programmable (OTP) bits. A first OTP register is used to change the scrambling of the secret key value whenever a lifecycle event occurs. A second OTP register is used to undo the change in the scrambling of the secret key. A third OTP register is used to affect a permanent change to the scrambling of the secret key. The scrambled values of the secret key (whether changed or unchanged) are used as seeds to produce keys for cryptographic operations by a device.

    HARDWARE CIRCUIT TO PERFORM ROUND COMPUTATIONS OF ARX-BASED STREAM CIPHERS
    43.
    发明申请
    HARDWARE CIRCUIT TO PERFORM ROUND COMPUTATIONS OF ARX-BASED STREAM CIPHERS 审中-公开

    公开(公告)号：US20180212761A1

    公开(公告)日：2018-07-26

    申请号：US15856682

    申请日：2017-12-28

    Applicant: Cryptography Research, Inc.

    Inventor： Begül Bilgin ,  Michael Hutter

    IPC: H04L9/06 ,  H04L9/08

    CPC classification number: H04L9/0631 ,  H04L9/0625 ,  H04L9/065 ,  H04L9/0861

    Abstract: Systems and methods for efficient computation of stream ciphers. An example system for implementing a stream cipher, may comprise: a sub-round computation circuit of a first type configured to perform a subset of transformations of a cipher computation round on a round input state, each transformation of the subset of transformations including at least one of: a bitwise addition operation, a bitwise exclusive disjunction operation, or a bitwise rotation operation. The sub-round computation circuit of the first type may comprise: one or more of sub-round computation circuits of a second type, wherein each sub-round computation circuit of the second type is configured to perform the subset of transformations of the cipher computation round on a respective part of the round input state.

    ASYMMETRICALLY MASKED MULTIPLICATION
    44.
    发明申请
    ASYMMETRICALLY MASKED MULTIPLICATION 审中-公开

    公开(公告)号：US20180211065A1

    公开(公告)日：2018-07-26

    申请号：US15935279

    申请日：2018-03-26

    Applicant: Cryptography Research, Inc.

    Inventor： JOSHUA M. JAFFE

    IPC: G06F21/72 ,  H04L9/00 ,  G06F7/72

    Abstract: Methods and systems for masking certain cryptographic operations in a manner designed to defeat side-channel attacks are disclosed herein. Squaring operations can be masked to make squaring operations indistinguishable or less distinguishable from multiplication operations. In general, squaring operations are converted into multiplication operations by masking them asymmetrically. Additional methods and systems are disclosed for defeating DPA, cross-correlation, and high-order DPA attacks against modular exponentiation.

    Methods and systems for glitch-resistant cryptographic signing
    46.
    发明授权
    Methods and systems for glitch-resistant cryptographic signing 有权
    防止恶意密码签名的方法和系统

    公开(公告)号：US09571289B2

    公开(公告)日：2017-02-14

    申请号：US14441998

    申请日：2013-11-11

    Applicant: CRYPTOGRAPHY RESEARCH INC.

    Inventor： Joshua M Jaffe

    IPC: G06F21/00 ,  H04L9/32 ,  H04L9/00 ,  H04L9/14

    CPC classification number: H04L9/3247 ,  H04L9/004 ,  H04L9/14 ,  H04L9/3252 ,  H04L2209/24 ,  H04L2209/72

    Abstract: Methods and devices disclosed herein use techniques to resist glitch attacks when computing discrete-log based signatures. The methods and systems described herein replace the random nonce in conventional signature systems with a pseudorandom nonce derived in a deterministic way from some internal state information, such as a secret key or a counter, such that the nonce is not repeated. The methods and systems described herein may also use tests to verify that a glitch has not occurred or been introduced.

    Abstract translation: 本文公开的方法和装置使用技术来抵抗在基于离散日志的签名时的毛刺攻击。 本文描述的方法和系统用诸如秘密密钥或计数器的某些内部状态信息以确定性方式导出的伪随机数替换常规签名系统中的随机随机数，从而不重复随机数。 本文描述的方法和系统还可以使用测试来验证毛刺没有发生或未被引入。

    VIRTUAL ONE-TIME PROGRAMMABLE MEMORY MANAGEMENT
    47.
    发明申请
    VIRTUAL ONE-TIME PROGRAMMABLE MEMORY MANAGEMENT 审中-公开
    虚拟一次性可编程内存管理

    公开(公告)号：US20160335196A1

    公开(公告)日：2016-11-17

    申请号：US15153624

    申请日：2016-05-12

    Applicant: Cryptography Research, Inc.

    Inventor： Ambuj Kumar ,  Roy Moss

    IPC: G06F12/10 ,  G06F3/06

    CPC classification number: G06F3/0673 ,  G06F3/0604 ,  G06F3/0665 ,  G06F12/0638 ,  G06F12/1036 ,  G06F2212/657

    Abstract: A virtual memory including virtual addresses may be generated. A first virtual address of the virtual memory may be mapped to a first physical address of a one-time programmable (OTP) memory of a device. Furthermore, a second virtual address of the virtual memory may be mapped to a second physical address of a static memory of the device. The virtual memory that is mapped to the OTP memory and the static memory may be provided for accessing of the data of the OTP memory of the device.

    Abstract translation: 可以生成包括虚拟地址的虚拟存储器。 可以将虚拟存储器的第一虚拟地址映射到设备的一次可编程（OTP）存储器的第一物理地址。 此外，虚拟存储器的第二虚拟地址可以映射到设备的静态存储器的第二物理地址。 映射到OTP存储器和静态存储器的虚拟存储器可以被提供用于访问设备的OTP存储器的数据。

    CONFIGURING A DEVICE BASED ON A DPA COUNTERMEASURE
    48.
    发明申请
    CONFIGURING A DEVICE BASED ON A DPA COUNTERMEASURE 审中-公开
    基于DPA计数器配置设备

    公开(公告)号：US20160315760A1

    公开(公告)日：2016-10-27

    申请号：US15135024

    申请日：2016-04-21

    Applicant: Cryptography Research, Inc.

    Inventor： Christopher Gori ,  Pankaj Rohatgi

    IPC: H04L9/00 ,  G06F21/75 ,  G06F21/72

    CPC classification number: H04L9/003 ,  G06F21/755 ,  G09C1/00 ,  H04L2209/08

    Abstract: Input signals may be received. Furthermore, a control signal controlling the implementation of a Differential Power Analysis (DPA) countermeasure may be received. One of the input signals may be transmitted as an output signal based on the control signal. A cryptographic operation may be performed based on the first output signal that is transmitted based on the control signal.

    Abstract translation: 可以接收输入信号。 此外，可以接收控制差分功率分析（DPA）对策的实现的控制信号。 可以基于控制信号将输入信号之一作为输出信号发送。 可以基于基于控制信号发送的第一输出信号来执行加密操作。

    Configurator for secure feature and key manager
    49.
    发明授权
    Configurator for secure feature and key manager 有权
    用于安全功能和密钥管理器的配置器

    公开(公告)号：US09436848B2

    公开(公告)日：2016-09-06

    申请号：US14289274

    申请日：2014-05-28

    Applicant: Cryptography Research, Inc.

    Inventor： Daniel Beitel ,  Lauren Gao ,  Christopher Gori ,  Paul Carl Kocher ,  Ambuj Kumar ,  Andrew John Leiserson

    IPC: G06F11/30 ,  G06F21/76 ,  G06F21/57

    CPC classification number: G06F21/76 ,  G06F21/572

    Abstract: A computing device receives a feature name or key name for an integrated circuit comprising a security manager core and an additional component. At least one of a) the additional component is associated with the key name or b) a feature provided by the additional component is associated with the feature name. The computing device receives a specified number of bits associated with the feature name or the key name, and maps the feature name to a feature address space or the key name to a key interface of the security manager core based at on the specified number of bits. The computing device generates at least one hardware description logic (HDL) module based on the mapping, wherein the at least one HDL module is usable to configure the security manager core for delivery of payloads associated with the feature name or the key name to the additional component.

    Abstract translation: 计算设备接收包括安全管理器核心和附加组件的集成电路的功能名称或密钥名称。 a）附加组件中的至少一个与密钥名称相关联，或者b）由附加组件提供的特征与特征名称相关联。 计算设备接收与特征名称或密钥名称相关联的指定数量的位，并且基于指定的位数将特征名称映射到特征地址空间或密钥名称到安全管理器核心的密钥接口 。 所述计算设备基于所述映射生成至少一个硬件描述逻辑（HDL）模块，其中所述至少一个HDL模块可用于配置所述安全管理器核心，用于将与所述特征名称或所述密钥名称相关联的有效载荷传递到所述附加 零件。

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