公开(公告)号：US07109544B2

公开(公告)日：2006-09-19

申请号：US10777128

申请日：2004-02-13

Applicant: Till Schloesser ,  Dirk Manger ,  Bernd Goebel

Inventor： Till Schloesser ,  Dirk Manger ,  Bernd Goebel

IPC: H01L27/108

CPC classification number: H01L27/10876 ,  H01L27/10823

Abstract: In a substrate vertical transistor cells are formed and are arranged, in a transistor cell array, row by row in an x direction and column by column in a y direction. Lower source/drain regions of the transistor cells are connected to a common connection plate. Upper source/drain regions of the transistor cells impart a contact connection for instance to a storage capacitor of a DRAM memory cell. Active trenches running between the transistor cells with word lines are formed along the x direction. The word lines form gate electrodes in sections. A potential at the gate electrode controls a conductive channel in an active region arranged in each case between the upper and the lower source/drain connection region. According to the invention, the active regions of adjacent transistor cells are sections of a contiguous layer body and are connected to one another. An accumulation of charge carriers in the active region and floating body effects are avoided without increasing the area requirement of a transistor cell.

Abstract translation: 在衬底中，垂直晶体管单元被形成并且在晶体管单元阵列中沿x方向逐行排列并且沿y方向逐列地排列。 晶体管单元的较低源极/漏极区域连接到公共连接板。 晶体管单元的上部源极/漏极区域例如向DRAM存储单元的存储电容器提供接触连接。 沿着x方向形成在具有字线的晶体管单元之间运行的有源沟槽。 字线形成栅电极。 在栅电极处的电位控制在每个情况下布置在上下源极/漏极连接区域之间的有源区中的导电沟道。 根据本发明，相邻晶体管单元的有源区是连续层体的部分并彼此连接。 在不增加晶体管单元的面积要求的情况下避免了有源区中的电荷载流子的积累和浮体效应。

公开(公告)号：US20050083724A1

公开(公告)日：2005-04-21

申请号：US10898706

申请日：2004-07-23

Applicant: Dirk Manger ,  Till Schloesser ,  Rolf Weis ,  Bernd Goebel ,  Wolfgang Mueller

Inventor： Dirk Manger ,  Till Schloesser ,  Rolf Weis ,  Bernd Goebel ,  Wolfgang Mueller

IPC: G11C11/34 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10867 ,  H01L27/10841 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/10891

Abstract: Memory cells each having a cell capacitor and a cell transistor, which are arranged in a vertical cell structure, are provided in the cell array of a DRAM. By means of a deep implantation or a shallow implantation and subsequent epitaxial growth of silicon, a buried source/drain layer is formed, from which lower source/drain regions of the cell transistors emerge. The upper edge of the buried source/drain layer can be aligned with respect to a lower edge of a gate electrode of the cell transistor and this results in a reduction of a gate/drain capacitance and also a leakage current between the gate electrode and the lower source/drain region. A body connection plate for the connection of the channel regions is applied to the substrate surface and contact holes are introduced into the body connection plate. Upper source/drain regions of the cell transistors are formed by implantation through the contact holes.

Abstract translation: 每个具有单元电容器和单元晶体管的存储单元被布置在垂直单元结构中，被提供在DRAM的单元阵列中。 通过深度注入或浅注入和随后的硅的外延生长，形成掩埋源极/漏极层，电池晶体管的下部源极/漏极区域从该衬底源极/漏极层出现。 掩埋源极/漏极层的上边缘可以相对于单元晶体管的栅电极的下边缘对齐，并且这导致栅极/漏​​极电容的减小以及栅电极和漏电极之间的漏电流 较低的源极/漏极区域。 用于连接通道区域的主体连接板被施加到基板表面，并且接触孔被引入主体连接板。 单元晶体管的上源/漏区通过接触孔注入而形成。

公开(公告)号：US06861688B2

公开(公告)日：2005-03-01

申请号：US10288387

申请日：2002-11-05

Applicant: Dirk Manger ,  Till Schlösser

Inventor： Dirk Manger ,  Till Schlösser

IPC: H01L21/4763 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/76

CPC classification number: H01L27/10888 ,  H01L27/10885

Abstract: A bit line configuration for contact-connecting at least one memory cell, in particular a DRAM memory cell, has bit lines disposed above the plane of the memory cell. A first bit line in a first bit line level is disposed below a second bit line in a second bit line level and the second bit line penetrates through the first bit line at at least one location of the first bit line for the purpose of producing a contact with the at least one memory cell at penetration locations. It is thus possible to provide space-saving structures, in particular sub-8F2 structures.

Abstract translation: 用于接触连接至少一个存储器单元，特别是DRAM存储单元的位线配置具有位于存储单元的平面之上的位线。 第一位线电平中的第一位线设置在第二位线电平中的第二位线下方，并且第二位线在第一位线的至少一个位置处穿过第一位线，以产生第 在穿透位置处与至少一个存储单元接触。 因此，可以提供节省空间的结构，特别是8F 2结构。

公开(公告)号：US20050001257A1

公开(公告)日：2005-01-06

申请号：US10777128

申请日：2004-02-13

Applicant: Till Schloesser ,  Dirk Manger ,  Bernd Goebel

Inventor： Till Schloesser ,  Dirk Manger ,  Bernd Goebel

IPC: H01L21/8239 ,  H01L21/8242 ,  H01L27/105 ,  H01L27/108

CPC classification number: H01L27/10876 ,  H01L27/10823

Abstract: In a substrate vertical transistor cells are formed and are arranged, in a transistor cell array, row by row in an x direction and column by column in a y direction. Lower source/drain regions of the transistor cells are connected to a common connection plate. Upper source/drain regions of the transistor cells impart a contact connection for instance to a storage capacitor of a DRAM memory cell. Active trenches running between the transistor cells with word lines are formed along the x direction. The word lines form gate electrodes in sections. A potential at the gate electrode controls a conductive channel in an active region arranged in each case between the upper and the lower source/drain connection region. According to the invention, the active regions of adjacent transistor cells are sections of a contiguous layer body and are connected to one another. An accumulation of charge carriers in the active region and floating body effects are avoided without increasing the area requirement of a transistor cell.

Abstract translation: 在衬底中，垂直晶体管单元被形成并且在晶体管单元阵列中沿x方向逐行排列并且沿y方向逐列地排列。 晶体管单元的较低源极/漏极区域连接到公共连接板。 晶体管单元的上部源极/漏极区域例如向DRAM存储单元的存储电容器提供接触连接。 沿着x方向形成在具有字线的晶体管单元之间运行的有源沟槽。 字线形成栅电极。 在栅电极处的电位控制在每个情况下布置在上下源极/漏极连接区域之间的有源区中的导电沟道。 根据本发明，相邻晶体管单元的有源区是连续层体的部分并彼此连接。 在不增加晶体管单元的面积要求的情况下避免了有源区中的电荷载流子的积累和浮体效应。